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This paper presents hybrid analog-to-digital converters (ADCs) using flash ADC and successive approximation register (SAR) ADC for improving conversion speed. The proposed architecture is the flash-hybrid-SAR architecture, which reduces the resolutio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b7bed8e8ed9fc234e5dc7329b8c79cc
https://doi.org/10.21203/rs.3.rs-2790201/v1
https://doi.org/10.21203/rs.3.rs-2790201/v1