Výsledky vyhledávání - "Ryoji Shiota"

Phase Noise Measurement and Testing with Delta-Sigma TDC

Autor: Sadayoshi Umeda, Haruo Kobayashi, Kiichi Niitsu, Takahiro Yamaguchi, Isao Shimizu, Tatsuji Matsuura, Naohiro Harigai, Masanobu Tsuji, Daiki Hirabayashi, Noriaki Dobashi, Osamu Kobayashi, Yusuke Osawa, Masafumi Watanabe, Ryoji Shiota, Nobukazu Takai

Publikováno v: Key Engineering Materials. 643:149-155

This paper describes a phase noise measurement and testing technique for a clock using a delta-sigma time-to-digital converter (TDC) and verifies its effectiveness with MATLAB simulations. The proposed technique can be implemented with relatively sma

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::024554c9188ce972341ad4f39903de82
https://doi.org/10.4028/www.scientific.net/kem.643.149

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SAR TDC architecture for one-shot timing measurement with full digital implementation

Autor: Takashi Ida, Haruo Kobayashi, Richen Jiang, Yuki Ozawa, Shotaro Sakurai, Ryoji Shiota, Rino Takahashi

Publikováno v: ISPACS

This paper proposes a successive approximation register (SAR) time-to-digital converter (TDC) architecture capable of measuring the timing difference between two single-shot signals with full digital FPGA. The SAR TDC is suitable for multi-channel ti

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fe26eeb86d538378b9000410debb0f23
https://doi.org/10.1109/ispacs.2017.8266523

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Study of jitter generators for high-speed I/O interface jitter tolerance testing

Autor: Ryoji Shiota, Haruo Kobayashi, Nobukazu Tsukiji, Takuya Arafune, Yuki Ozawa

Publikováno v: ISPACS

This paper proposes two low-cost jitter generators for high-speed I/O interface jitter tolerance testing. (i) The first one uses inter-symbol interference positively with digital control. The proposed circuit consists of mostly digital circuits with

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::02ac1a0e78f9234ccdf46615447c0033
https://doi.org/10.1109/ispacs.2017.8266524

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SAR TDC Architecture with Self-Calibration Employing Trigger Circuit

Autor: Shotaro Sakurai, Ryoji Shiota, Haruo Kobayashi, Takashi Ida, Seiya Takigami, Nobukazu Tsukiji, Yuki Ozawa, Richen Jiang

Publikováno v: ATS

This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for timing built-in self-test (BIST) / built-out self-test (BOST) implementation. In order to reduce the number of buffers and D Flip-Flops (DFFs) in a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::085de21f6539419448ed81a7b5285589
https://doi.org/10.1109/ats.2017.29

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Gray-code input DAC architecture for clean signal generation

Autor: Dan Yao, Yuki Ozawa, Ryoji Shiota, Nobukazu Tsukiji, Rino Takahashi, Yifei Sun, Haruo Kobayashi, Richen Jiang, Gopal Adhikari

Publikováno v: ISPACS

This paper describes digital-to-analog converter (DAC) architectures for clean signal generation used in such as arbitrary waveform generators (AWGs) as well as graphic displays; the clean signal is applied to analog/mixed-signal/RF devices for testi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::773eeca97a20d85a645a524503b35a31
https://doi.org/10.1109/ispacs.2017.8266561

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Study of multistage digital oscilloscope trigger circuit

Autor: Seiya Takigami, Nobukazu Tsukiji, Yuki Ozawa, Ryoji Shiota, Takashi Ida, Yasunori Kobori, Shotaro Sakurai, Haruo Kobayashi

Publikováno v: ISPACS

This paper describes a general equation of the input and output relation in N-stage configuration of a trigger circuit, which outputs a sine wave (or a cosine wave) with a zero phase at the timing when a trigger signal input is applied. Its conventio

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2bb698a310f1294c23922decd999cce1
https://doi.org/10.1109/ispacs.2017.8266560

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Architecture of high performance successive approximation time digitizer

Autor: Ryoji Shiota, Takashi Ida, Yuki Ozawa, Haruo Kobayashi, Jiang Richen, Shotaro Sakurai, Hirotaka Arai, Nobukazu Tsukiji, Seiya Takigami

Publikováno v: ISPACS

This paper describes three techniques for a high performance successive-approximation-register time-to-digital converter (SAR TDC) measuring the time difference between two timing signals. (1) Two-step SAR TDC configuration for fine time resolution a

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::1e8d17537393e31595329601e167b879
https://doi.org/10.1109/ispacs.2017.8266522

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Timing measurement BOST architecture with full digital circuit and self-calibration using characteristics variation positively for fine time resolution

Autor: Ryoji Shiota, Congbing Li, Junshan Wang, Haruo Kobayashi

Publikováno v: 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW).

This paper presents a time-to-digital converter (TDC) architecture to measure the timing difference between single-event two pulses with fine time resolution. Its features are as follows: (i) The architecture is based on stochastic process and statis

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::15301abfaaccf9f133d9058ed7c231d7
https://doi.org/10.1109/ims3tw.2016.7524228

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Successive approximation time-to-digital converter with vernier-level resolution

Autor: Congbing Li, Haruo Kobayashi, Richen Jiang, Mayu Hirano, Kazumi Hatayama, Yuki Ozawa, Nobukazu Tsukiji, Mingcong Yang, Ryoji Shiota

Publikováno v: 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW).

This paper presents a time-to-digital converter (TDC) architecture with reduced hardware suitable for multichannel timing built-out self-test (BOST) implementation on an FPGA chip. In order to reduce the number of buffers and DFFs in a conventional F

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2c5b1b92188be12f829d1ea1eff4d1cf
https://doi.org/10.1109/ims3tw.2016.7524226

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