Zobrazeno 1 - 10
of 60
pro vyhledávání: '"Russell P. Kraft"'
Autor:
Ryan Clarke, Philip Jacob, Okan Erdogan, Paul Belemijian, Srikumar Raman, Mitchell R. Leroy, Tuhin Guha Neogi, Russell P. Kraft, Diana-Andra Borca-Tasciuc, John F. McDonald
Publikováno v:
IEEE Access, Vol 3, Pp 43-54 (2015)
We have previously evaluated the feasibility of a serial code accelerator core with 3-D DRAM stacked on the core operating at high frequencies. While operating at such high frequencies (>24 GHz), there are concerns with removing heat from the 3-D sta
Externí odkaz:
https://doaj.org/article/0e37535f0afa4f08ab5422b299d0d98f
Autor:
Mitchell R. LeRoy, Tuhin Guha Neogi, Russell P. Kraft, Ryan Clarke, John F. McDonald, Srikumar Raman
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:2703-2713
Many design challenges exist in achieving high frequency clocking for high-speed applications. This paper describes a new clock distribution technique and clocking approach with the use of clock doublers in close proximity to sub-circuits to achieve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ce53eb1ecd6beb7c05c66b49516c6ce
https://doi.org/10.1109/jssc.2015.2472600
https://doi.org/10.1109/jssc.2015.2472600
Autor:
Philip Jacob, Paul Belemijian, John F. McDonald, Okan Erdogan, Diana-Andra Borca-Tasciuc, Mitchell R. LeRoy, Tuhin Guha Neogi, Srikumar Raman, Ryan Clarke, Russell P. Kraft
Publikováno v:
IEEE Access, Vol 3, Pp 43-54 (2015)
We have previously evaluated the feasibility of a serial code accelerator core with 3-D DRAM stacked on the core operating at high frequencies. While operating at such high frequencies (>24 GHz), there are concerns with removing heat from the 3-D sta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c26a6e2ef08c942d5bb52078754d5c6a
https://doi.org/10.1109/access.2015.2396474
https://doi.org/10.1109/access.2015.2396474
Autor:
Ryan Clarke, Mitchell R. LeRoy, John F. McDonald, Russell P. Kraft, Michael Chu, Hadrian Olayvar Aquino, Aamir Zia, Srikumar Raman, Xuelian Liu
Publikováno v:
IET Circuits, Devices & Systems. 8:487-498
This study documents the speeds of various SRAM buffer memories that are possible in a contemporary fast SiGe heterojunction bipolar transistor (HBT) BiCMOS process. An SRAM in a 0.13 µm HBT BiCMOS technology using current mode logic (CML)-style cir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f7ba06b877c8365959ba832f019a11a6
https://doi.org/10.1049/iet-cds.2013.0375
https://doi.org/10.1049/iet-cds.2013.0375
Autor:
Mitchell R. LeRoy, John F. McDonald, Russell P. Kraft, Srikumar Raman, A. Gutin, Michael Chu, Okan Erdogan, Xuelian Liu, Ryan Clarke
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 61:178-182
The time needed for processing serial code in programs has become the performance bottleneck of multicore computer systems according to Amdahl's law. A high-speed clock rate processor is essential for processing this serial code. The register file is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::078dff6d2d0b61f6b155efba64c38a20
https://doi.org/10.1109/tcsii.2013.2296119
https://doi.org/10.1109/tcsii.2013.2296119
Autor:
John F. McDonald, P. M. Belemjian, Michael Chu, A. Gutin, Russell P. Kraft, Mitchell R. LeRoy, Philip Jacob
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 58:2201-2210
Adder structures utilizing SiGe Hetero-junction Bipolar Transistor (HBT) digital circuits are examined for use in high clock rate digital applications requiring high-speed integer arithmetic. A 4-gate deep test structure for 32-bit addition using a 2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::790d4dc7595dd16288b1234df5bdb4dd
https://doi.org/10.1109/tcsi.2011.2112850
https://doi.org/10.1109/tcsi.2011.2112850
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:967-977
Slow cache memory systems and low memory bandwidth present a major bottleneck in performance of modern microprocessors. 3-D integration of processor and memory subsystems provides a means to realize a wide data bus that could provide a high bandwidth
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02c5aaff9b1021031804a823baeda4ed
https://doi.org/10.1109/tvlsi.2009.2017750
https://doi.org/10.1109/tvlsi.2009.2017750
Autor:
Mitchell R. LeRoy, Philip Jacob, John F. McDonald, Jin-Woo Kim, Michael Chu, Russell P. Kraft
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:380-390
The search for high speed, high bandwidth A/D converters is ongoing, and techniques to push the envelope are constantly being developed. In this paper an open loop, scalable, time-interleaved ADC architecture is presented, as well as a 60 GHz Colpitt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7b06518944a42b1f52582bfd321616b
https://doi.org/10.1109/jssc.2009.2039375
https://doi.org/10.1109/jssc.2009.2039375
Autor:
Okan Erdogan, Jin-Woo Kim, Aamir Zia, Russell P. Kraft, P.M. Belemjian, John F. McDonald, K. Bernstein, Philip Jacob, Michael Chu
Publikováno v:
Proceedings of the IEEE. 97:108-122
Three-dimensional chip (3-D) stacking technology provides a new approach to address the so-called memory wall problem. Memory processor chip stacking reduces this memory wall problem, permitting faster clock rates (with suitable processor logic) or p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88d04e15a7f5ec91983829980a77aec0
https://doi.org/10.1109/jproc.2008.2007472
https://doi.org/10.1109/jproc.2008.2007472
Publikováno v:
Proceedings of the IEEE. 93:1669-1678
A major impediment to the continuation of Moore's Law in the years to come is the performance of interconnections in ICs at high frequencies. Microprocessors are using a greater portion of their clock cycle charging and discharging interconnections.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2ba48e522f043a2dcb01969d9e085067
https://doi.org/10.1109/jproc.2005.852548
https://doi.org/10.1109/jproc.2005.852548