Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Rupesh S. Shelar"'
Autor:
Rupesh S. Shelar
Publikováno v:
FPGA
Logic replication is often necessary to improve speed of emulation for systems employing field programmable gate arrays (FPGAs), since design sizes are large enough requiring partitioning to fit a design into multiple (boards of) FPGAs. In this paper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81c28792322203df926fab89ddd9c993
https://doi.org/10.1145/3373087.3375356
https://doi.org/10.1145/3373087.3375356
Autor:
Marek Patyra, Rupesh S. Shelar
Publikováno v:
ISPD
In nanometer technologies, even local interconnects are believed to cause major impact on timing, power, repeaters, and routability in VLSI circuits. Although empirical studies exist, there is little comprehensive work that explores the impact of loc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f8b562bcda9b034163aa697ba9028eef
https://doi.org/10.1109/tcad.2013.2266404
https://doi.org/10.1109/tcad.2013.2266404
Autor:
Rupesh S. Shelar
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 31:1781-1786
Clocks are known to be major source of power consumption in digital circuits. In this paper, we propose a clustering algorithm for the minimization of power in a local clock tree. Given a set of sequentials and their locations, clustering is performe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2af593957c073113f0292378df339acd
https://doi.org/10.1109/tcad.2012.2206592
https://doi.org/10.1109/tcad.2012.2206592
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30:416-426
Technology mapping and placement have a significant impact on delays in standard cell-based very large scale integrated circuits. Traditionally, these steps are applied separately to optimize the delays, possibly since efficient algorithms that allow
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f182a4cec820e5c7141691c6f2b1fdd1
https://doi.org/10.1109/tcad.2010.2089569
https://doi.org/10.1109/tcad.2010.2089569
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:625-636
Routing congestion has become a serious concern in today's very-large-scale-integration designs. To address this, the authors propose a technology mapping algorithm that minimizes routing congestion under delay constraints in this paper. The algorith
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::792fb7d474276c077bf509aaa709ba2e
https://doi.org/10.1109/tcad.2006.870078
https://doi.org/10.1109/tcad.2006.870078
Autor:
Sachin S. Sapatnekar, Rupesh S. Shelar
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 13:957-970
We address the problem of synthesizing pass transistor logic (PTL), with the specific objective of delay reduction, through binary decision diagram (BDD) decomposition. The decomposition is performed by mapping the BDD to a network flow graph, and th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06ac893ea00275a27e97a1e9e00c431b
https://doi.org/10.1109/tvlsi.2005.853601
https://doi.org/10.1109/tvlsi.2005.853601
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 24:696-710
Due to increasing design complexities, routing congestion has become a critical problem in very large scale integration designs. This paper introduces a distributed metric to predict routing congestion and applies it to technology mapping that target
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8d5ea05e5c3b99c627a37bbdd63b0adc
https://doi.org/10.1109/tcad.2005.846368
https://doi.org/10.1109/tcad.2005.846368
Autor:
Rupesh S. Shelar
Publikováno v:
ISPD
In modern microprocessors, clocks are usually distributed employing a hybrid network, grid followed by buffered trees, to restrict the skew. This is typically done employing (gated) buffered trees inside the blocks, while the global grid overlay the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02686ac596a35da5fa9fa5e9b3705b55
https://doi.org/10.1145/1514932.1514964
https://doi.org/10.1145/1514932.1514964
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization
Publikováno v:
2008 IEEE/ACM International Conference on Computer-Aided Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4123467b17e7429487d8d6a1ec7bbd87
https://doi.org/10.1109/iccad.2008.4681558
https://doi.org/10.1109/iccad.2008.4681558
Autor:
Rupesh S. Shelar
Publikováno v:
ISPD
Clocks are known to be major source of power consumption in digital circuits, especially in high performance microprocessors. With the technology scaling, the increasingly capacitive interconnects contribute to more than 40% of the local clock power.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1bf30283db61517cfc0177dd16cef62
https://doi.org/10.1145/1231996.1232037
https://doi.org/10.1145/1231996.1232037