Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Run Levinger"'
Publikováno v:
IEEE Microwave Magazine. 23:71-85
Publikováno v:
2021 IEEE MTT-S International Microwave Symposium (IMS).
This paper demonstrates a low power, compact and wideband oscillator design that is based on a transformer coupled feedback (TCF). The digitally controlled oscillator (DCO) was implemented in a commercial CMOS finfet process and covers 8.83-14.38GHz,
Autor:
Mark Elzinga, Ashoke Ravi, Edwin Thaller, Rotem Banin, Run Levinger, Kamran Azadet, Christian Krassnitzer, Sergey Bershansky, Christoph Duller, Aryeh Farber, Jasmin Kadry, Gil Horovitz, Evgeny Shumaker, Patrick Torta, Nir Geron
Publikováno v:
ISSCC
The demand for massive MIMO, digital beamforming, and increased bandwidth communication dramatically increases the complexity of the remote radio head in future cellular base-stations. This complexity issue can be addressed by RF transceiver SoCs inc
Autor:
Elan Banin, Gil Horovitz, Evgeny Shumaker, N. Geron, Run Levinger, Ofir Degani, S. Bershansky, J. Kadry, Aryeh Farber, Rotem Banin, Ashoke Ravi
Publikováno v:
2020 50th European Microwave Conference (EuMC).
This paper presents a power efficient sub-sampling all-digital phase-locked loop with less than 90fsrms jitter performance. A stochastic-flash time-to-digital converter is utilized and obtains sub-picosecond effective resolution. A "folded" common mo
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:1328-1337
The implementation of wideband mm-wave radars for automotive applications necessitates wideband, fast, and precise linear frequency modulation generation. In this paper, we propose to use dual-loop phase-locked loop (PLL) architecture for this task.
Publikováno v:
2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
This paper presents two X-band state of the art digitally controlled oscillators (DCO’s), one utilizes CMOS and the other NMOS as cross-coupled pairs. Both designs include a "folded" common-mode resonator in order to enhance performance while minim
Publikováno v:
2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF).
This paper presents an ultra-low power all-digital phase-locked loop (ADPLL) with 543 fs rms jitter. Fabricated in a commercial 28-nm CMOS technology, the ADPLL covers 3.95-to-4.685 GHz (17% fractional tuning range). Measured phase noise (PN) at 100
Publikováno v:
IEEE Transactions on Microwave Theory and Techniques. 64:1078-1087
Two fully integrated chipsets covering the entire E-band frequency range, 71–76/81–86 GHz, have been demonstrated. These designs, which were implemented in 0.13- $\mu{\hbox{m}}$ SiGe BiCMOS technology, use a sliding IF superheterodyne architectur
Autor:
Danny Elad, Benny Sheinman, Oded Katz, Run Levinger, Roee Ben-Yishay, Eli Bloch, N. Mazor, Roi Carmon
Publikováno v:
IEEE Microwave and Wireless Components Letters. 27:401-403
A linear RF to IF downconversion and IF to RF upconversion mixers for 60-GHz transceivers were implemented in 0.13- $\mu \text{m}$ SiGe technology. The mixers were implemented using a mixing core only topology for enhanced linearity, with no local os
Publikováno v:
2018 13th European Microwave Integrated Circuits Conference (EuMIC).
This paper presents an LC tank, ultra-low power CMOS digitally controlled oscillator (DCO) with resistive drain delay element designed and fabricated in 28 nm CMOS process. The implemented DCO covers 3.95 to 4.7 GHz (17% tuning range, TR) with a reso