Automatic debugging of System-on-a-Chip designs.

Autor: Rogin, F., Drechsler, R., Rulke, S.

Publikováno v: 2009 IEEE International SOC Conference (SOCC); 2009, p333-336, 4p

High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs.

Autor: Boden, M., Fiebig, T., Meissner, T., Rulke, S., Becker, J.

Publikováno v: 2007 IEEE International Parallel & Distributed Processing Symposium; 2007, p1-8, 8p

IPQ: IP qualification for efficient system design.

Autor: Brand, H.-J., Rulke, S., Radetzki, M.

Publikováno v: International Symposium on Signals, Circuits & Systems. Proceedings, SCS 2003. (Cat. No.03EX720); 2004, p478-482, 5p

Enhanced reusability for SoC-based HW/SW co-design.

Autor: Boden, M., Schneider, J., Feske, K., Rulke, S.

Publikováno v: Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods & Tools; 2002, p94-99, 6p

Low power design of FSMs by state assignment and disabling self-loops.

Autor: Koegst, M., Franke, G., Rulke, S., Feske, K.

Publikováno v: EUROMICRO 97 Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat No97TB100167); 1997, p323-330, 8p