Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Rui Murakami"'
Autor:
Masashi Shinagawa, Yasufumi Hino, Masaya Miyahara, Shinya Tamonoki, Yasuo Asakura, Yuuki Tsukui, Toshihiko Ito, Ryo Minami, Kenichi Okada, Ning Li, N. Shimasaki, Hiroyuki Yamagishi, Rui Murakami, Ahmed Eleojo Musa, Akira Matsuzawa, Takashi Sato, T. Yamaguchi, Makoto Noda, Hironori Sakaguchi, Kouta Matsushita, Keigo Bunsen, Keitarou Kondou, Qinghong Bu, Hiroki Asada, Yasuaki Takeuchi
Publikováno v:
IEEE Journal of Solid-State Circuits. 48(No. 1):46-65
This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is ca
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. (No. 2):506-514
This paper proposes a dual-conduction class-C VCO for ultra-low supply voltages. Two cross-coupled NMOS pairs with different bias points are employed. These NMOS pairs realize an impulse-like current waveform to improve the phase noise in the low sup
Publikováno v:
IEICE Electronics Express. 8:512-517
This paper proposes an ultra compact LC-VCO. Due to the speed-up of CMOS digital circuits, jitter of ring oscillators is becoming a critical problem. Even though an LC-VCO has a better phase noise, a layout size of on-chip inductor is a problem as a
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science. (No. 2):424-430
SUMMARY The multiple-divide technique, using the multi-ratio frequency divider, has a possibility to improve FoM of VCO. This paper proposes a design optimization of LC-VCO using the multiple-divide technique. In the simulated results using 90-nm CMO
Publikováno v:
IEICE Transactions on Electronics. :777-784
SUMMARY In this paper we present a study on the design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by the quality factor of inductors. It has been experimentally shown that higher-Q indu
Autor:
Yuki Tsukui, Ahmed Eleojo Musa, Qinghong Bu, Hiroki Asada, Takahiro Sato, Rui Murakami, Yasuaki Takeuchi, Masaya Miyahara, Seitaro Kawai, Ryo Minami, Kenichi Okada, Akira Matsuzawa, Ning Li
Publikováno v:
2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC).
This paper presents a digitally-calibrated 60-GHz direct-conversion transceiver. To improve the error vector magnitude (EVM) performance over the wide bandwidth, a digital calibration technique is applied. The 60-GHz transceiver implemented by 65 nm
Autor:
Shinya Tamonoki, Yasuo Asakura, Makoto Noda, Qinghong Bu, Masaya Miyahara, Tatsuya Yamaguchi, Hironori Sakaguchi, Ahmed Eleojo Musa, Hiroki Asada, Akira Matsuzawa, Yuuki Tsukui, Ryo Minami, Kenichi Okada, Keigo Bunsen, Ning Li, Hiroyuki Yamagishi, Rui Murakami, Toshihiko Ito, Yasuaki Takeuchi, Yasufumi Hino, Masashi Shinagawa, Naoki Shimasaki, Takahiro Sato, Kota Matsushita, Keitarou Kondou
Publikováno v:
ISSCC
This paper presents a 60GHz direct-conversion front-end and baseband transceiver, including analog and digital circuitry for the PHY functions. The 65nm CMOS front-end consumes 319mW and 223mW in transmitting and receiving mode, respectively, and is
Autor:
Hiroki Asada, Takahiro Sato, Akira Matsuzawa, Rui Murakami, Toshihiko Ito, Ryo Minami, Kenichi Okada, Kota Matsushita, Ahmed Eleojo Musa, Keigo Bunsen, Qinghong Bu, Tatsuya Yamaguchi
Publikováno v:
A-SSCC
This paper presents a 16QAM direct-conversion transceiver in 65nm CMOS, which is capable of 60-GHz wireless standards. The capacitive cross-coupling neutralization contributes a high common-mode rejection and a high reverse isolation, and a fully-bal
Autor:
Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa
Publikováno v:
2011 IEEE International Solid-State Circuits Conference.
Autor:
Akira Matsuzawa, Rui Murakami, Takahiro Sato, Ahmed Eleojo Musa, Win Chiavipas, Kenichi Okada
Publikováno v:
2010 IEEE Asian Solid-State Circuits Conference.
This paper proposes a 60GHz quadrature PLL frequency synthesizer that has a tuning range capable of covering the whole band specified by the IEEE802.15.3c with exceptional phase noise. The synthesizer is constructed using a 20GHz PLL that is coupled