Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Ruey-Lian Hwang"'
Autor:
Peter Ramvall, A. Devin Giddings, Yee-Chia Yeo, Aryan Afzalian, Ruey-Lian Hwang, T. Vasen, Matthias Passlack
Publikováno v:
ACS Applied Nano Materials. 2:1253-1258
Growth of ultrathin semiconducting nanowires (NWs) and incorporation of dopants suitable for future CMOS scaling targets (diameter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90e51991d43be422c5ec28df5c2148aa
https://doi.org/10.1021/acsanm.8b02092
https://doi.org/10.1021/acsanm.8b02092
Autor:
Giddings, A. Devin, Ramvall, Peter, Vasen, Tim, Afzalian, Aryan, Ruey-Lian Hwang, Yee-Chia Yeo, Passlack, Matthias
Publikováno v:
ACS Applied Nano Materials; 3/22/2019, Vol. 2 Issue 3, p1253-1258, 6p
Autor:
Baw-Ching Perng, Renee Huang, M.S. Liang, S.M. Jang, Li-Chien Chen, Ruey-Lian Hwang, Joe Hsu, David Fong, Jyu-Horng Shieh
Publikováno v:
SPIE Proceedings.
The need for absolute accuracy is increasing as semiconductor-manufacturing technologies advance to sub-65nm nodes, since device sizes are reducing to sub-50nm but offsets ranging from 5nm to 20nm are often encountered. While TEM is well-recognized a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d69fc2d16d25849bcab9dc3538b2b7f1
https://doi.org/10.1117/12.655986
https://doi.org/10.1117/12.655986
Publikováno v:
International Symposium for Testing and Failure Analysis.
Device shrinkage has resulted in thinner barriers and smaller vias. Transmission Electron Microscopy (TEM) has become a common technique for barrier profile analysis because of its high image resolution. TEM sample preparation and image interpretatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::607eba8487debe34c74d32353f5b288c
https://doi.org/10.31399/asm.cp.istfa2002p0689
https://doi.org/10.31399/asm.cp.istfa2002p0689
Publikováno v:
International Symposium for Testing and Failure Analysis.
This paper presents the results of a study on yield loss in wafers produced using a 0.25-μm CMOS process. It describes how the authors determined that a short in the M1 metal layer was the major yield killer and how they traced the cause to excess C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::02d1637e9e380bde65798f21101aeff4
https://doi.org/10.31399/asm.cp.istfa2000p0117
https://doi.org/10.31399/asm.cp.istfa2000p0117