Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Rudy Beraha"'
Autor:
Danny Butterfield, Chunlei Shi, Rashid Ahmed Akbar Attar, Karam S. Chatha, Ken Easton, Yu Pu, Mark Lin, Venkat Rangan, Rudy Beraha, Adam E. Newham, Giby Samson, Dongkyu Park
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:936-948
This paper gives an overview of the Blackghost 1.0 system-on-chip (SoC) from Qualcomm Research, which was our first test chip that paved the way toward the commercialization of Qualcomm’s most recent ultra-low-power Blackghost SoC family. Specifica
Autor:
Chunlei Shi, Yu Pu, Ken Easton, Rashid Ahmed Akbar Attar, Adam E. Newham, Rudy Beraha, Yang Du
Publikováno v:
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
We introduce the Blackghost 1.0 SoC developed in Qualcomm Research, which is our first test chip that paved the road towards the commercialization of the ultra-low-Vdd Blackghost product family. Through seamless integration of many low-power innovati
Autor:
J. Kumar, S. Namasivayam, H. Sheraji, V. Ganesan, Aghera Parixit Laljibhai, J. Hadi, J. Fatehi, Ken Easton, Rashid Ahmed Akbar Attar, R. McLaren, Rudy Beraha, Karam S. Chatha, Giby Samson, M. Derkalousdian, Chunlei Shi, Dongkyu Park, E. Arvelo, Yu Pu, Adam E. Newham, D. Butterfield, Mark Lin, Ravindra Vaman Shenoy
Publikováno v:
COOL Chips
This paper introduces the Blackghost 1.0, which is a test chip that paved the way for Qualcomm's newest Blackghost ultra-low-power mixed-signal SoC product family. Specifically targeted at battery-powered Internet-of-Things, wearables and e-medical a
Publikováno v:
ISQED
Network-on-Chip (NoC) architectures have been widely adopted as the preferred solution to the communication challenges of System-on-Chip (SoC) design in the nanoscale regime. SoC designs often incorporate custom NoC architectures that do not conform
Publikováno v:
Low Power Networks-on-Chip ISBN: 9781441969101
Low Power Networks-on-Chip
Low Power Networks-on-Chip
In this chapter, we examine the design process of a network on-chip (NoC) for a high-end commercial system on-chip (SoC) application. We present several design choices and focus on the power optimization of the NoC while achieving the required perfor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f8af42feb49d750c5aee15df83290a0
https://doi.org/10.1007/978-1-4419-6911-8_7
https://doi.org/10.1007/978-1-4419-6911-8_7
Publikováno v:
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).