Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Roy Emek"'
Publikováno v:
HLDVT
This paper reports on the verification models of twelve systems including servers and advanced processors. We focus on system-level stimuli generation and study reuse in subsequent system models. The paper describes our modeling framework, where syst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3983a15c4e00b33861f35d8a4dc9e8e5
https://doi.org/10.1109/hldvt.2005.1568822
https://doi.org/10.1109/hldvt.2005.1568822
Publikováno v:
DAC
Multimedia SoCs are characterized by a main controller that directs the activity of several cores, each of which is in charge of a stage in the processing of a media stream. The verification of these SoCs is a significant challenge due to time-to-mar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2aaabd220db5b95440627ba2db1b352a
https://doi.org/10.1145/1146909.1146999
https://doi.org/10.1145/1146909.1146999
Autor:
Yehuda Naveh, Roy Emek
Publikováno v:
Principles and Practice of Constraint Programming-CP 2005 ISBN: 9783540292388
CP
CP
Functional verification of modern hardware design consumes roughly 70% of the effort invested in the design cycle. Simulation of randomly generated stimuli is the main means of achieving functional verification. A typical verification effort is cente
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f20e2fdf502e656b2a5d80d1fdac45e
https://doi.org/10.1007/11564751_120
https://doi.org/10.1007/11564751_120
Publikováno v:
MTV
We present a new test case generation technology, specifically targeted at verifying systems that include address translation mechanisms. The ever-growing demand for performance makes these mechanisms more complex, thereby increasing the risk of bugs
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::60c31f3ab5dffd731d0f28ad8b345653
https://doi.org/10.1109/mtv.2003.1250255
https://doi.org/10.1109/mtv.2003.1250255
Autor:
Roy Emek, Yehuda Naveh
Publikováno v:
HLDVT
We present a methodology for scheduling system-level transactions generated by a test-case generator. A system, in this context, may be composed of multiple processors, busses, bus-bridges, memories, etc. The methodology is based on an exploration of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f7fff0aa22466dfa9019ac35c2f8575d
https://doi.org/10.1109/hldvt.2003.1252489
https://doi.org/10.1109/hldvt.2003.1252489
Autor:
Monica Farkash, Alex Goldin, Itai Jaeger, Yehuda Naveh, I. Dozoretz, G. Aloni, Roy Emek, Yoav Katz, G. Bergman
Publikováno v:
HLDVT
We present X-Gen, a model-based test-case generator designed for systems and systems on a chip (SoC). X-Gen provides a framework and a set of building blocks for system-level test-case generation. At the core of this framework lies a system model, wh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d153aaca4291ec9634d661af1549c397
https://doi.org/10.1109/hldvt.2002.1224444
https://doi.org/10.1109/hldvt.2002.1224444
Publikováno v:
HLDVT
Simulation of automatically-generated test programs is the primary means for verifying complex hardware designs and random test program generators therefore play a major role in the verification process of micro-processors. The input for a test progr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b774da1a0c07895822309db2e3ff998
https://doi.org/10.1109/hldvt.2002.1224433
https://doi.org/10.1109/hldvt.2002.1224433
Conference
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