Zobrazeno 1 - 10
of 118
pro vyhledávání: '"Routing congestion"'
Publikováno v:
IEEE Access, Vol 10, Pp 65971-65981 (2022)
Continued scaling in accordance with Moore’s law is becoming increasingly difficult. Pitch shrinkage and standard cell height reduction via design technology co-optimization with design rules have sustained this scaling until recently. However, we
Externí odkaz:
https://doaj.org/article/bdca7c1885e04fe0b1c71b223a500dd4
Autor:
Osama Bin Tariq, Junnan Shan, Georgios Floros, Christos P. Sotiriou, Mario R. Casu, Mihai Teodor Lazarescu, Luciano Lavagno
Publikováno v:
IEEE Access, Vol 9, Pp 54286-54297 (2021)
Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While software developers can use h
Externí odkaz:
https://doaj.org/article/db168a37c1c041648add24fffb055994
Akademický článek
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Autor:
Prasun Datta, Shyamapada Mukherjee
Publikováno v:
Analog Integrated Circuits and Signal Processing. 109:501-515
In this paper, an optimized placement approach has been presented for mixed-size designs. A novel initial placement approach is introduced to achieve routability-aware global placement using new routability-aware cell clustering, cluster positioning,
Publikováno v:
Journal of Electronic Testing. 36:239-253
In 3D IC, wrapper chains can span across vertical directions which causes the increase in number of TSVs(through-silicon-vias)(which is used to interconnect different cores in the vertical directions). Excessive use of TSVs in wrapper design causes r
Autor:
Pingakshya Goswami, Dinesh Bhatia
Publikováno v:
Electronics, Vol 10, Iss 1995, p 1995 (2021)
Electronics
Volume 10
Issue 16
Electronics
Volume 10
Issue 16
Design closure in general VLSI physical design flows and FPGA physical design flows is an important and time-consuming problem. Routing itself can consume as much as 70% of the total design time. Accurate congestion estimation during the early stages
Publikováno v:
ISCAS
Circuits that are placed with very low (or high) aspect ratio are susceptible to routing overflows. Such designs are difficult to close and usually end up with larger area with low area utilization. We observe that non-uniform setting of utilization
Publikováno v:
VLSI-DAT
With the increasing complexity of the design rules, the routability has become one of the most essential factors that should be considered in the placement stage; however, being the routable basis of the placer in the past, the congestion map given b
Publikováno v:
Applied Reconfigurable Computing. Architectures, Tools, and Applications ISBN: 9783030790240
ARC
ARC
Virtual FPGA (V-FPGA) architectures are useful as both early prototyping testbeds for custom FPGA architectures, as well as to enable advanced features which may not be available on a given host FPGA. V-FPGAs use standard FPGA synthesis and placement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::24df72c11fb247345dfef530e48dbca1
https://publikationen.bibliothek.kit.edu/1000136813
https://publikationen.bibliothek.kit.edu/1000136813
Autor:
Vaibbhav Taraate
Publikováno v:
ASIC Design and Synthesis ISBN: 9789813346413
If we consider the moderately complex designs to perform the general processor applications or floating-point applications then if the architecture is designed by considering the optimization goals, then during the physical design, we will have few c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f68359160304990c8b56eb77c55ba16
https://doi.org/10.1007/978-981-33-4642-0_17
https://doi.org/10.1007/978-981-33-4642-0_17