Zobrazeno 1 - 10
of 769
pro vyhledávání: '"Rossetti, D"'
Autor:
Ammendola, R., Biagioni, A., Frezza, O., Lonardo, A., Cicero, F. Lo, Martinelli, M., Paolucci, P. S., Pastorelli, E., Rossetti, D., Simula, F., Tosoratto, L., Vicini, P.
Publikováno v:
Jinst February 3, 2015
The APEnet+ board delivers a point-to-point, low-latency, 3D torus network interface card. In this paper we describe the latest generation of APEnet NIC, APEnet v5, integrated in a PCIe Gen3 board based on a state-of-the-art, 28 nm Altera Stratix V F
Externí odkaz:
http://arxiv.org/abs/2201.01088
Autor:
Ammendola, R., Biagioni, A., Cretaro, P., Di Lorenzo, S., Fantechi, R., Fiorini, M., Frezza, O., Lamanna, G., Cicero, F. Lo, Lonardo, A., Martinelli, M., Neri, I., Paolucci, P. S., Pastorelli, E., Piandani, R., Pontisso, L., Rossetti, D., Simula, F., Sozzi, M., Vicini, P.
Over the last few years the GPGPU (General-Purpose computing on Graphics Processing Units) paradigm represented a remarkable development in the world of computing. Computing for High-Energy Physics is no exception: several works have demonstrated the
Externí odkaz:
http://arxiv.org/abs/1606.04099
Autor:
Lonardo, A., Ameli, F., Ammendola, R., Biagioni, A., Frezza, O., Lamanna, G., Cicero, F. Lo, Martinelli, M., Paolucci, P. S., Pastorelli, E., Pontisso, L., Rossetti, D., Simeone, F., Simula, F., Sozzi, M., Tosoratto, L., Vicini, P.
While the GPGPU paradigm is widely recognized as an effective approach to high performance computing, its adoption in low-latency, real-time systems is still in its early stages. Although GPUs typically show deterministic behaviour in terms of latenc
Externí odkaz:
http://arxiv.org/abs/1406.3568
Autor:
Ammendola, R., Biagioni, A., Frezza, O., Lamanna, G., Lonardo, A., Cicero, F. Lo, Paolucci, P. S., Pantaleo, F., Rossetti, D., Simula, F., Sozzi, M., Tosoratto, L., Vicini, P.
NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34 Gbps APElink channel. The design has GPUDirect RDMA capabilities and features a network stack protocol offloading module, making it suitable for building low-latency,
Externí odkaz:
http://arxiv.org/abs/1311.4007
Autor:
Ammendola, R., Biagioni, A., Chiodi, G., Frezza, O., Cicero, F. Lo, Lonardo, A., Lunadei, R., Paolucci, P. S., Rossetti, D., Salamon, A., Salina, G., Simula, F., Tosoratto, L., Vicini, P.
Publikováno v:
JINST 5:C12019,2010
We present test results and characterization of a data transmission system based on a last generation FPGA and a commercial QSFP+ (Quad Small Form Pluggable +) module. QSFP+ standard defines a hot-pluggable transceiver available in copper or optical
Externí odkaz:
http://arxiv.org/abs/1103.0128
Publikováno v:
PoS LAT2005 (2005) 100
We present the current status of APENet, our custom 3-dimensional interconnect architecture for PC clusters environment. We report some micro-benchmarks on our recent large installation as well as new developments on the software and hardware side. T
Externí odkaz:
http://arxiv.org/abs/hep-lat/0509130
Publikováno v:
In Journal of Parallel and Distributed Computing April 2018 114:28-45
Autor:
Ammendola, R., Guagnelli, M., Mazza, G., Palombi, F., Petronzio, R., Rossetti, D., Salamon, A., Vicini, P.
Developed by the APE group, APENet is a new high speed, low latency, 3-dimensional interconnect architecture optimized for PC clusters running LQCD-like numerical applications. The hardware implementation is based on a single PCI-X 133MHz network int
Externí odkaz:
http://arxiv.org/abs/hep-lat/0409071
Autor:
Bodin, F., Boucaud, Ph., Cabibbo, N., Di Carlo, F., De Pietri, R., Di Renzo, F., Kaldass, H., Lonardo, A., Lukyanov, M., De Luca, S., Micheli, J., Morenas, V., Pene, O., Pleiter, D., Paschedag, N., Rapuano, F., Rossetti, D., Sartori, L., Schifano, F., Simma, H., Tripiccione, R., Vicini, P.
Publikováno v:
ECONF C030626:FRAP15,2003
We present the APE (Array Processor Experiment) project for the development of dedicated parallel computers for numerical simulations in lattice gauge theories. While APEmille is a production machine in today's physics simulations at various sites in
Externí odkaz:
http://arxiv.org/abs/hep-lat/0309007
Autor:
Bodin, F., Boucaud, Ph., Micheli, J., Pene, O., Cabibbo, N., Di Carlo, F., Lonardo, A., de Luca, S., Rapuano, F., Rossetti, D., Vicini, P., De Pietri, R., Di Renzo, F., Kaldass, H., Paschedag, N., Simma, H., Morenas, V., Pleiter, D., Sartori, L., Schifano, F., Tripiccione, R.
Publikováno v:
ECONF C0303241:THIT005,2003
We present the current status of the apeNEXT project. Aim of this project is the development of the next generation of APE machines which will provide multi-teraflop computing power. Like previous machines, apeNEXT is based on a custom designed proce
Externí odkaz:
http://arxiv.org/abs/hep-lat/0306018