Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Rose George Kunthara"'
Publikováno v:
SN Computer Science. 4
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72c9136ecaa244d1bdc153367861fdf2
https://doi.org/10.1007/s42979-022-01622-y
https://doi.org/10.1007/s42979-022-01622-y
Publikováno v:
2022 IEEE 19th India Council International Conference (INDICON).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::685226981363e5cab6484889fa788a23
https://doi.org/10.1109/indicon56171.2022.10039775
https://doi.org/10.1109/indicon56171.2022.10039775
Publikováno v:
Proceedings of the Great Lakes Symposium on VLSI 2022.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::883e1de1b8f5265904e38ce1c9b593a8
https://doi.org/10.1145/3526241.3530332
https://doi.org/10.1145/3526241.3530332
Publikováno v:
VDAT
Network-on-Chip (NoC) has been a viable solution for resolving the complexities associated with inter-processor communications in a Chip Multi Processor (CMP). NoC accounts for a significant portion of the total power consumed by a CMP. In a standard
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2d0d124f799f54598f8f64a7b7cea99
https://doi.org/10.1109/vdat53777.2021.9601003
https://doi.org/10.1109/vdat53777.2021.9601003
Publikováno v:
2021 8th International Conference on Smart Computing and Communications (ICSCC).
Many-core processors are widely used in areas such as cloud computing, big data processing, high performance computing and data centre applications. Network on Chip (NoC) is the preferred interconnect solution which can overcome scalability issues an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b235521a0216b68f805e12395bb11d6
https://doi.org/10.1109/icscc51209.2021.9528183
https://doi.org/10.1109/icscc51209.2021.9528183
Publikováno v:
NoCArc@MICRO
Network on Chip (NoC) concept has evolved as a standard design approach for integrating large number of processing cores within a single die. The performance improvements which occur due to topological optimizations and architectural enhancements of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1422b1aa1d6e30f5afc8ee7bdeb2fef9
https://doi.org/10.1145/3356045.3360720
https://doi.org/10.1145/3356045.3360720
Publikováno v:
TENCON
Network on Chip (NoC) is embraced as an interconnect solution for the design of large tiled chip multiprocessors (TCMP). Bufferless NoC router is a promising approach due to its simple router design, energy and hardware efficiency. NoC, which rely on
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2865c82bb319afa53929b3ab92eb62ca
https://doi.org/10.1109/tencon.2019.8929475
https://doi.org/10.1109/tencon.2019.8929475
Autor:
Tripti S. Warrier, Rose George Kunthara, Rekha K. James, K Neethu, John Jose, Simi Zerine Sleeba
Publikováno v:
Communications in Computer and Information Science ISBN: 9789813297661
VDAT
VDAT
The rise in complexity and number of processing cores in SoC has paved way to the development of efficient and structured on-chip communication framework known as Network on Chip (NoC). NoC is embraced as an interconnect solution for the design of la
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9f888b639d02e108413afd2f8df0f88
https://doi.org/10.1007/978-981-32-9767-8_27
https://doi.org/10.1007/978-981-32-9767-8_27
Publikováno v:
Nano Communication Networks. 27:100334
Network-on-Chip (NoC) has emerged as a cost-effective on-chip interconnects solution for Tiled Chip Multi Processors (TCMP) where many computational cores occupy a single chip. The performance of NoC network can be greatly enhanced by incorporating 3
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b4c22c9641283e4736c6e740ac933033
https://doi.org/10.1016/j.nancom.2020.100334
https://doi.org/10.1016/j.nancom.2020.100334
Publikováno v:
ISED
Network on Chip (NoC) is emerging as a promising design paradigm as an on-chip interconnect for multi-core architectures to overcome scalability and bottleneck issues of traditional bus-based and point-to-point communication architectures. Minimum pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba610db9cbbbda47b19ecd55b115a890
https://doi.org/10.1109/ised.2018.8704012
https://doi.org/10.1109/ised.2018.8704012