Zobrazeno 1 - 10
of 208
pro vyhledávání: '"Ronald F. Demara"'
Autor:
Muhtasim Alam Chowdhury, Mousam Hossain, Christopher Mastrangelo, Ronald F. DeMara, Soheil Salehi
Publikováno v:
Frontiers in Electronics, Vol 5 (2024)
Hardware-based acceleration approaches for Machine Learning (ML) workloads have been embracing the significant potential of post-CMOS switching devices to attain reduced footprint and/or energy-efficient execution relative to transistor-based GPU and
Externí odkaz:
https://doaj.org/article/dc0a9a94d9e44ad8b969a641b5477922
Autor:
Hossein Pourmeidani, Ronald F. Demara
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 7, Iss 2, Pp 125-131 (2021)
Two-terminal magnetoresistive random access memory (MRAM) devices provide a recent approach to intrinsically realizing stochastic neuronal behavior in cognitive architectures such as restricted Boltzmann machines (RBMs) for deep belief networks (DBNs
Externí odkaz:
https://doaj.org/article/da222e16512b49659d0eb142e2eb88d5
Autor:
Shadi Sheikhfaal, Ronald F. Demara
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 6, Iss 1, Pp 62-70 (2020)
Biological memory structures impart enormous retention capacity while automatically providing vital functions for chronological information management and update the resolution of the domain and episodic knowledge. A crucial requirement for hardware
Externí odkaz:
https://doaj.org/article/ccfde5d676bf4f9e957288e4f328d040
Publikováno v:
Micromachines, Vol 13, Iss 10, p 1738 (2022)
Deep learning methods have exhibited the great capacity to process object detection tasks, offering a practical and viable approach in many applications. When researchers have advanced deep learning models to improve their performance, the model deri
Externí odkaz:
https://doaj.org/article/a43d00c59b894a7bb2f87b3b913ca1c0
Publikováno v:
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol 5, Iss 1, Pp 43-51 (2019)
The neural sampling core (NSC) proposed herein offers a spintronic device-based circuit and learning mechanism utilizing imprecise and stochastic components, similar to biological brains, to realize ultralow-power neuromorphic computations at subthre
Externí odkaz:
https://doaj.org/article/bb8c8371ed284c7eaf5eb84bd3acc570
Publikováno v:
IEEE Access, Vol 7, Pp 55851-55860 (2019)
During recent years, researchers throughout academia and industry have been advancing the theory, designing, and applications of mobile service computing through the Internet of Things (IoT). Research interest in mobile service computing stems from i
Externí odkaz:
https://doaj.org/article/c5d9b05f7b0b46acb566899c1d238f77
Autor:
Navid Khoshavi, Ronald F. Demara
Publikováno v:
IEEE Access, Vol 6, Pp 14576-14590 (2018)
As capacity and complexity of on-chip cache memory hierarchy increases, the service cost to the critical loads from last level cache (LLC), which are frequently repeated, has become a major concern. The processor may stall for a considerable interval
Externí odkaz:
https://doaj.org/article/ec1d954b4af148c4a423cc12bf3bd0f3
Publikováno v:
IEEE Access, Vol 4, Pp 2863-2872 (2016)
Mixed-signal system-on-chip (SoC) devices offer single-chip solutions, but face challenges of hardware-software co-design optimization, device signal range constraints, and limited precision. These issues are addressed by developing a multi-level evo
Externí odkaz:
https://doaj.org/article/9972448db5384c8780b2ebaeb4053cc9
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 5, Iss 1, Pp 3-37 (2015)
This paper considers the problem of how to efficiently measure a large and complex information field with optimally few observations. Specifically, we investigate how to stochastically estimate modular criticality values in a large-scale digital circ
Externí odkaz:
https://doaj.org/article/4eb6469a66d240aa87ef899b232ec93c
Autor:
Naveed Imran, Ronald F. DeMara
Publikováno v:
International Journal of Reconfigurable Computing, Vol 2014 (2014)
Distance-Ranked Fault Identification (DRFI) is a dynamic reconfiguration technique which employs runtime inputs to conduct online functional testing of fielded FPGA logic and interconnect resources without test vectors. At design time, a diverse set
Externí odkaz:
https://doaj.org/article/1af39122b5664cd58d0c222782d0a57e