Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Ronald D. Goldblatt"'
Autor:
M. Guillorn, Deqiang Wang, Steve Rossnagel, Lynne Gignac, Qinghuang Lin, Sung-Wook Nam, Ajay K. Royyuru, Robert L. Bruce, Gustavo Stolovitzky, P. J. Litwinowicz, Armand Galan, Dirk Pfeiffer, Evan G. Colgan, Ronald D. Goldblatt, S. Papa Rao, J.J. Bucchignano, Markus Brink, Michael F. Lofaro, Chao Wang, W. H. Advocate, Elizabeth A. Duch, E. Kratschmer, C. M. Breslin, John M. Cotte, William Henry Price, Christopher V. Jahnes, Stas Polonsky, Hongbo Peng, Eric A. Joseph
Publikováno v:
2013 IEEE International Electron Devices Meeting.
We report sub-20 nm sacrificial nanochannels that enable stretching and translocating single DNA molecules. Sacrificial silicon nano-structures were etched with XeF2 to form nanochannels. Translocations of linearized DNA single molecules were imaged
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7009e4a7a92742f8a8752e24815c32d7
https://doi.org/10.1109/iedm.2013.6724627
https://doi.org/10.1109/iedm.2013.6724627
Autor:
David Kramer, Gerard M. Salem, Ronald D. Goldblatt, J. Corr, Robert M. Houle, D. Cawthron, P. McCormick, Paul D. Kartschoke, M. Canada, R. Schulz, J. Bialas, Norman J. Rohrer, R. Floyd, Stephen Frank Geissler, Bijan Davari, Chekib Akrout, L. Su, L. Whitney
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1609-1616
A 32 b 480 MHz PowerPC reduced-instruction-set-computer (RISC) microprocessor is migrated into an advanced 0.2 /spl mu/m CMOS technology with copper interconnects and multi-threshold transistors. These technology features have helped to increase the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4d18cd66c0f624317b5947f8de6b7e3
https://doi.org/10.1109/4.726544
https://doi.org/10.1109/4.726544
Autor:
John E. Heidenreich, Luis M. Ferreiro, Richard R. Thomas, Sharon L. Nunes, T. H. Chao, Ned J. Chou, Leena Paivikki Buchwalter, Ronald D. Goldblatt
Publikováno v:
Journal of Applied Polymer Science. 46:2189-2202
To enhance polyimide-to-polyimide adhesion, we have investigated the effect of surface modification in water vapor plasma. The use of a water vapor plasma to treat a fully cured polyimide (PMDA–ODA) surface before subsequent layers of polyimide are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1ee80182fb15a64bf01b52c091a82ff9
https://doi.org/10.1002/app.1992.070461216
https://doi.org/10.1002/app.1992.070461216
Autor:
W. Lai, Steven J. Holmes, Werner A. Rausch, Allen H. Gabor, Karl Paul Muller, Colin J. Brodsky, Ernest Y. Wu, Jeffrey J. Welser, Sujatha Sankaran, Ricardo A. Donaton, S. Wu, Ronald A. DellaGuardia, S.K.H. Fung, W. Yan, S.H. Ku, Steven W. Mittl, Anthony I. Chou, A. Vayshenker, J. Snare, Paul D. Agnello, Len Y. Tsou, Mukesh Khare, Michael A. Gribelyuk, Renee T. Mo, Robert J. Purtell, F. Jamin, P.A. McFarland, Akihisa Sekiguchi, D. Nielsen, D. Wehella-Gamage, Ronald D. Goldblatt, E. Barth, Richard A. Ferguson, Tina Wagner, Dominic J. Schepis, Shreesh Narasimha, Woo-Hyeong Lee, Bruce B. Doris, Percy V. Gilbert, Stephen E. Greco, X. Chen, Sadanand V. Deshpande, Yujun Li
Publikováno v:
Digest. International Electron Devices Meeting.
This paper presents a high performance 90 nm generation SOI CMOS logic technology. Leveraging unique SOI technology features, aggressive ground rules and a tungsten local interconnect rendered the smallest 6T SRAM cell reported to date with a cell ar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a76288235c918aa108b3bc11283b3430
https://doi.org/10.1109/iedm.2002.1175865
https://doi.org/10.1109/iedm.2002.1175865
Autor:
H. Ng, J. Oberschmidt, Michael J. Hargrove, Ronald D. Goldblatt, X. Chen, Deborah A. Ryan, E. J. Nowak, K. Tallman, T. Wagner, Stephen E. Greco, C. DeWan, Bijan Davari, E. Barth, J. Connolly, Klaus Dietrich Beyer, Richard A. Ferguson, Paul D. Agnello, P. McLaughlin, Emmanuel F. Crabbe, S. Crowder, R. Logan, Vincent J. McGahay, Robert J. Purtell, L. Su, Asit Kumar Ray, G. A. Biery
Publikováno v:
1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).
In this paper, we describe a high-performance 0.18 /spl mu/m logic technology with dual damascene copper metallization and dense SRAM memory. Local interconnect technology allows us to fabricate SRAM cells as small as 3.84 /spl mu/m/sup 2/. We demons
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b2f55f6d9842bd12f56888f942545bc
https://doi.org/10.1109/vlsit.1999.799362
https://doi.org/10.1109/vlsit.1999.799362
Autor:
John J. Ritsko, W. Volksen, W. Graham, Donald C. Hofer, Richard P Mcgouey, J. W. Labadie, Sharon L. Nunes, J. L. Hedrick, Eileen A. Galligan, Katherine L. Saenger, G.V. Kopcsay, Jurij R. Paraszczak, Ronald D. Goldblatt, Russell J. Serino, Edward D. Babich, David F. Witman, Helen Li Yeh, Vincent Ranieri, Laura Beth Rothman, D. Y. Shih, Chandrasekhar Narayan, Janusz S. Wilczynski, J. Cataldo, Alina Deutsch, J. M. Shaw
Publikováno v:
1991 Proceedings 41st Electronic Components & Technology Conference.
Multilayer copper/polyimide interconnect structures were fabricated using a reactive-ion-etching-based lift-off technique. Conductor cross-sectional area control, planarity, and a gap-free structure were made possible by the use of a novel siloxane-p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78e9616fb680851b0094716eb1116ab8
https://doi.org/10.1109/ectc.1991.163901
https://doi.org/10.1109/ectc.1991.163901
Autor:
G. Hellner, H. Harrer, G. A. Biery, L. Su, Emmanuel F. Crabbe, C.W. Surovic, Alina Deutsch, Paul W. Coteus, N.A. Greco, Ronald D. Goldblatt, Daniel C. Edelstein, D.M. Foster
Publikováno v:
International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
Experimental high-speed characterization and electrical modeling and simulation are presented for a six-layer Cu/SiO/sub 2/ on-chip wiring structure with 12.4-mm-long lines. Testing is performed over the temperature range -160/spl deg/C to +100/spl d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d77e04c8f5c5e0d101e9dbff2f42d756
https://doi.org/10.1109/iedm.1998.746358
https://doi.org/10.1109/iedm.1998.746358
Autor:
E. Eld, R. Schulz, T. Wagner, Daniel C. Edelstein, Janet S. Herman, William J. Cote, C. Guenther, L. Su, H. Ng, John E. Heidenreich, R. Gehres, K. Beyer, N. Greco, C. Megivern, Asit Kumar Ray, J. Oberschmidt, G. A. Biery, J. McKenna, D. Kiesling, Bijan Davari, D. Foster, Ronald D. Goldblatt, Norman J. Rohrer, K. Tallman, J. Ellis-Monaghan, Emmanuel F. Crabbe, James W. Adkisson, S.-H. Lo, L. Lin
Publikováno v:
1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).
A sub-0.25 /spl mu/m technology in manufacturing that is targeted for high-performance CMOS applications is discussed. Aggressive groundrule scaling including SRAM cell size down to 5.4 /spl mu/m/sup 2/ is combined with multiple threshold voltage dev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::63495eea98cb264eda546d513ed0cc30
https://doi.org/10.1109/vlsit.1998.689182
https://doi.org/10.1109/vlsit.1998.689182
Autor:
A.K. Stamper, T. Katsetos, P. C. Andricacos, John E. Heidenreich, Stephen E. Luce, John Owen Dukovic, Ronald D. Goldblatt, Naftali E. Lustig, Richard A. Wachnik, J. Slattery, Daniel C. Edelstein, A. Simon, Thomas L. McDevitt, H. S. Rathore, Cyprian E. Uzoh, William J. Cote, P. McLaughlin
Publikováno v:
Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
Recently, IBM announced the implementation of a full copper interconnect scheme which will be manufactured on its high-performance 0.20 /spl mu/m CMOS products later this year. Features of this technology are presented here, as well as functional ver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::847939bd04f73a3e4baee4d7e4937c68
https://doi.org/10.1109/iitc.1998.704776
https://doi.org/10.1109/iitc.1998.704776
Autor:
L. Su, Naftali E. Lustig, John E. Heidenreich, Cyprian E. Uzoh, Peter Roper, Stephen E. Luce, R. Schulz, Richard A. Wachnik, William J. Cote, A. Simon, Ronald D. Goldblatt, J. Dukovic, W. Motsiff, J. Slattery, Daniel C. Edelstein, H. Rathore, Thomas L. McDevitt
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
We present the first fully integrated ULSI CMOS/copper interconnect technology. Up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a polycontacted pitch of 0.81 /spl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::562fb72b2e9b5262a16ac9dec8cab0e7
https://doi.org/10.1109/iedm.1997.650496
https://doi.org/10.1109/iedm.1997.650496