Zobrazeno 1 - 1
of 1
pro vyhledávání: '"Ron Tsechanski"'
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 61:1095-1104
This work presents a novel approach based on gate-level analysis for implementing Selective State Retention Power Gating (SSRPG). A selective SRPG approach mitigates the area and power overhead of the conventional SRPG technique. However, only very f