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pro vyhledávání: '"Ron Kapusta"'
Autor:
Ron Kapusta
Publikováno v:
IEEE Solid-State Circuits Magazine. 10:112-115
Presents information on the 2018 Symposium on VLSI Technology and Circuits: Technology, Circuits, and Systems for Smart Living.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::647b5a43fbd023242c078a3c425f114a
https://doi.org/10.1109/mssc.2018.2867142
https://doi.org/10.1109/mssc.2018.2867142
Autor:
Ron Kapusta
Publikováno v:
IEEE Solid-State Circuits Magazine. 9:136-140
Presents information on the 2017 Symposium on VLSI Circuits: Harmonious Integration Toward Next Dimensions.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0279b29352d38c3baf2f17a7148ae2be
https://doi.org/10.1109/mssc.2017.2746197
https://doi.org/10.1109/mssc.2017.2746197
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:1707-1715
The conventional switched-capacitor amplifier faces design tradeoffs between settling accuracy and noise, in that high settling accuracy demands wide bandwidth but at the sacrifice of noise performance. In fact settling accuracy and noise exhibit dif
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70ee904afe7d1c3fa0385a2002c91e64
https://doi.org/10.1109/tcsi.2015.2446540
https://doi.org/10.1109/tcsi.2015.2446540
Autor:
Mark D. Maddox, Ned Guthrie, Michael C. W. Coln, Nikhil Mascarenhas, Ron Kapusta, Lalinda D. Fernando, Junhua Shen, Baozhen Chen, Akira Shikata
Publikováno v:
2017 Symposium on VLSI Circuits.
This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) that is much smaller and faster than other recently reported precision (16-bit and beyond) SAR ADCs. In addition, it features low input capacitance and an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1de2e74a04519126301a8684ea260ed7
https://doi.org/10.23919/vlsic.2017.8008509
https://doi.org/10.23919/vlsic.2017.8008509
Publikováno v:
ISSCC
A 14-bit SAR ADC is presented that achieves 73.6 dB SNDR at 80 MSPS while using a 1.2-V-only supply. In order to overcome throughput limitations common to conventional SAR ADCs, several techniques are proposed. First, a flash sub-ADC is utilized to r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d20216dc9da5711dc97d1009cd61284a
https://doi.org/10.1109/jssc.2013.2274113
https://doi.org/10.1109/jssc.2013.2274113
Autor:
Michael C. W. Coln, Baozhen Chen, Mark D. Maddox, Lalinda D. Fernando, Junhua Shen, Ron Kapusta
Publikováno v:
A-SSCC
This paper presents a first reported passive-charge-sharing SAR ADC that achieves 16 bit linearity. It is known that on chip passive-charge-sharing suffers from poor linearity due to the unregulated reference voltage during bit trials. The proposed u
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::63d4a87b55e24eac7157f77d1e3a5343
https://doi.org/10.1109/asscc.2016.7844158
https://doi.org/10.1109/asscc.2016.7844158
Autor:
Ron Kapusta
Publikováno v:
CICC
• Time-interleaved SAR ADCs are a major focus of active development • Power and area efficiency of SAR architecture suits itself very well to interleaving • Architecture scale well with advancing CMOS process — Process-limited FOM S (jitter)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e2ef236ac187483ef4ab119617eba76
https://doi.org/10.1109/cicc.2015.7338441
https://doi.org/10.1109/cicc.2015.7338441
Publikováno v:
CICC
Several circuit-level techniques are described which are used to reduce or cancel thermal noise and break the so-called kT/C limit. kT/C noise describes the total thermal noise power added to a signal when a sample is taken on a capacitor. In the fir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::870eb721d868083797ec8019233cf3fc
https://doi.org/10.1109/cicc.2013.6658440
https://doi.org/10.1109/cicc.2013.6658440
Autor:
Ron Kapusta, Eric Naviasky
Publikováno v:
CICC
This session on Nyquest rate data converters has 7 exciting papers exploring the ranges of low power pipeline converters, calibration of SAR converters, ultra high speed flash converters, and high speed low power interleaved SAR converters.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b164cd8448d20fb44b6f16cc597c10c7
https://doi.org/10.1109/cicc.2009.5280854
https://doi.org/10.1109/cicc.2009.5280854