Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Romain Brillu"'
Autor:
Romain Brillu, Pillement Sebastien, Philippe Millet, Frodoric Falzon, Fabrice Lemonnier, Marc Bernot, Eric Lenormand
Publikováno v:
Euromicro Conference on Parallel, Distributed, and Network-Based Processing
Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP'2014)
Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP'2014), Feb 2014, Turin, Italy. pp.PDP PID3016521
PDP
Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP'2014)
Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP'2014), Feb 2014, Turin, Italy. pp.PDP PID3016521
PDP
International audience; The deployment of an application onto a multicore architecture is often a long and difficult process. This is due to the fact that the characteristics of both the architecture and the application are taken into account late in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b6c0c53b77d981149f57af7f6bb2966c
https://hal.archives-ouvertes.fr/hal-00913758
https://hal.archives-ouvertes.fr/hal-00913758
Publikováno v:
Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools (RAPIDO 2014)
Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools
Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools, Jan 2014, Vienne, Austria. pp.RAPIDO 2014
RAPIDO
Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools
Workshop on Rapid Simulation & Performance Evaluation: Methods and Tools, Jan 2014, Vienne, Austria. pp.RAPIDO 2014
RAPIDO
International audience; This paper introduces the FlexTiles platform, which consist of a manycore architecture associated with a complete tool ow. The di erent components of the manycore architecture are based on general purpose processors (GPP), low
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4ed1f58eacb8f7d9068cff2ec106d470
https://hal.archives-ouvertes.fr/hal-00913778
https://hal.archives-ouvertes.fr/hal-00913778
Publikováno v:
Design Automation for Embedded Systems
Design Automation for Embedded Systems, Springer Verlag, 2013, 17 (3), pp 587-607. ⟨10.1007/s10617-014-9146-5⟩
Design Automation for Embedded Systems, 2013, 17 (3), pp 587-607. ⟨10.1007/s10617-014-9146-5⟩
Design Automation for Embedded Systems, Springer Verlag, 2013, 17 (3), pp 587-607. ⟨10.1007/s10617-014-9146-5⟩
Design Automation for Embedded Systems, 2013, 17 (3), pp 587-607. ⟨10.1007/s10617-014-9146-5⟩
International audience; This paper proposes a hardware memory management unit to implement an on-chip message passing protocol for cluster based multi-processors system on chip architectures. Within the architecture each cluster is composed of genera
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6ad5685fdca3425b8fb39a5d3b980875
https://hal.archives-ouvertes.fr/hal-01058600
https://hal.archives-ouvertes.fr/hal-01058600
Publikováno v:
DATE'2013
Design, Automation & Test in Europe
Design, Automation & Test in Europe, Mar 2013, Grenoble, France. Friday Workshop on Reconfigurable Computing V2.0: The Next Generation of Technology, Architectures a
HAL
Design, Automation & Test in Europe
Design, Automation & Test in Europe, Mar 2013, Grenoble, France. Friday Workshop on Reconfigurable Computing V2.0: The Next Generation of Technology, Architectures a
HAL
International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::3b0802d59d5c38b74444df5cceafcdee
https://hal.science/hal-00808400
https://hal.science/hal-00808400
Publikováno v:
HAL
France, Patent n° : FR3025334. 2016, Dépôt FR20140001942 le 2/09/2014
United States, Patent n° : US2016063164. 2016, pp.EXTENSION BREVET FRANCE FR3025334
France, Patent n° : FR3025334. 2016, Dépôt FR20140001942 le 2/09/2014
United States, Patent n° : US2016063164. 2016, pp.EXTENSION BREVET FRANCE FR3025334
The invention relates to a method for determining by optimization a multi-core architecture and a way of implementing an application on the architecture for a given application, the method comprising: providing a parallelized application and candidat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::ac1fec6d860201a866e62ba3ebedca30
https://hal.archives-ouvertes.fr/hal-01096731
https://hal.archives-ouvertes.fr/hal-01096731