Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Rolf Sautter"'
Autor:
Otto Dipl.-Ing. Torreiter, J. Pille, Michael Kugel, Rolf Sautter, A. Frisch, P. Salz, Gordon B. Sapp, Amira Rozenfeld, Eric Fluhr, Jens Noack, Thomas Kalla, M. Lee, D. Wendel, Wolfgang Penth
Publikováno v:
ESSCIRC
The POWER9™ Processor in 14 nm SOI FinFET technology makes use of 7 different families of arrays. This paper gives an overview on advantages of different implementations, focusing on two key innovations introduced with this processor generation: Fa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f65efdbf7f35ef89cdf04ad3364e3b0
https://doi.org/10.1109/esscirc.2017.8094586
https://doi.org/10.1109/esscirc.2017.8094586
Autor:
Rolf Sautter, Juergen Pille, Dieter Wendel, Shankar Kalyanasundaram, Daniel A. Dobson, Alexander Fritsch, Michael Kugel, Otto Torreiter
Publikováno v:
ESSCIRC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f2c974139dbc90c1c24a325a0bd9e973
https://doi.org/10.1109/esscirc.2015.7313897
https://doi.org/10.1109/esscirc.2015.7313897
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1628-1635
To address the challenges in microprocessor designs beyond a gigahertz, an instruction window buffer (IWB) was designed. The IWB implements the processor parts for renaming, reservation station, and reorder buffer as a unified buffer. Measured result
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4dbd701285d88bfb6ddd8a1634a3d751
https://doi.org/10.1109/4.962282
https://doi.org/10.1109/4.962282
Autor:
Fadi H. Gebara, D. Wendel, J.B. Kuang, Jeremy D. Schaub, S. Saroop, Tuyen V. Nguyen, B. Lloyd, C.M. Durham, J. Pille, Kevin J. Nowka, A. Muller, Sani R. Nassif, B. Robbins, T. Frohnel, Rolf Sautter
Publikováno v:
CICC
Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0aeb174b09931e07d1230503d185e22a
https://doi.org/10.1109/cicc.2010.5617630
https://doi.org/10.1109/cicc.2010.5617630
Autor:
Otto Wagner, Juergen Pille, Jose Angel Paredes, Stefan Buettner, M. Canada, Thomas Froehnel, Rolf Sautter, David Scott Ray, Otto Torreiter, Martin Eckert, David A. Hrusecky, Dieter Wendel, Wolfgang Penth
Publikováno v:
ISSCC
Increasing demand for parallelism due to out-of-order and multi-threading computation requires fast and dense arrays with multi-port capabilities. The load-store-unit (LSU) of the POWER7™ microprocessor core has a 32kB L1 data cache composed of fou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f48529f0c91954422deea2ba23dd3fdd
https://doi.org/10.1109/isscc.2010.5433849
https://doi.org/10.1109/isscc.2010.5433849
Autor:
Donald W. Plass, Rajiv V. Joshi, Timothy J. Charest, Rolf Sautter, Daniel Rodko, R. Freese, Philip George Shephard, Y.-H. Chan, Tobias Werner, Pradip Patel, Uma Srinivasan, William V. Huott
Publikováno v:
2006 IEEE international SOI Conferencee Proceedings.
An embedded CMOS static random access memory (SRAM), including the array and a method of accessing cells in the array with improved cell stability for scalability and performance (over 5 GHz) is demonstrated in hardware using 65 nm Partially Depleted
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26cc9f89008a9d48537ef1fa8ee94833
https://doi.org/10.1109/soi.2006.284405
https://doi.org/10.1109/soi.2006.284405
Autor:
Juergen Pille, S. Buttner, N. Mading, Rolf Sautter, Sebastian Ehrenreich, Jens Leenstra, Wilhelm Haller
Publikováno v:
DATE Designers' Forum
A vector fixed point unit (FXU) is designed to speed up multimedia processing. The FXU implements SIMD style integer arithmetic and permute operations. The adder, rotator and permute structure enables the use of static circuits only. The FXU was fabr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a91c57b96cb886deef86c681c914cb6e
https://doi.org/10.1109/date.2006.243933
https://doi.org/10.1109/date.2006.243933
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
An Instruction Window Buffer (IWB) addresses the challenges in microprocessor designs beyond a GHz. The IWB implements the processor parts for renaming, reservation station and reorder buffer as a unified buffer. Measured results on an experimental c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d0d63fa2228a9871f1880e36a2328ca9
https://doi.org/10.1109/isscc.2001.912653
https://doi.org/10.1109/isscc.2001.912653