Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Roland Jancke"'
Publikováno v:
ATZ worldwide. 125:56-61
Publikováno v:
ATZ - Automobiltechnische Zeitschrift. 125:56-61
Autor:
André Lange, Fabio A. Velarde Gonzalez, Kay-Uwe Giering, Anastasios Vervantidis, Lukas Hahne, Andy Heinig, Roland Jancke
Publikováno v:
Microelectronics Reliability. 137:114775
The importance of integrated circuit (IC) reliability has been growing to benefit from the potentials of advanced semiconductor technologies in long-living applications, such as automotive electronics. Today, prototypes and products are tested for th
Publikováno v:
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
DATE
DATE
In this work we present a technology for dynamically introducing fault structures into digital twins without the need to change the virtual prototype model. The injection is done at the beginning of a simulation by dynamically rewiring the involved n
Publikováno v:
SMARTGREENS
Autor:
R.-P. Vollertsen, Hans Reisinger, Tibor Grasser, G. Rott, Gerhard Rzepa, Katja Puschkarsky, Roland Jancke, Kay-Uwe Giering
We investigate the negative-bias temperature instability (NBTI) degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages and thereby generalize existing digital-stress NBTI studies. Starting from our ultrafast NB
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::057d6c41b784ea39e4579e9cea7b7889
https://publica.fraunhofer.de/handle/publica/257221
https://publica.fraunhofer.de/handle/publica/257221
Autor:
Asen Asenov, Andre Lange, Binjie Cheng, Roland Jancke, Christoph Sohrmann, Ulf Schlichtmann, Joachim Haase
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:197-210
Process variations and atomic-level fluctuations increasingly pose challenges to the design and analysis of integrated circuits by introducing variability. Although several approaches have been proposed to deal with the inherent statistical nature of
Publikováno v:
ICCAD
Electromigration (EM) is becoming a progressively severe reliability challenge due to increased interconnect current densities. A shift from traditional (post-layout) EM verification to robust (pro-active) EM-aware design - where the circuit layout i
Autor:
S. Schlipf, G. Kurz, A. Aal, Ehrenfried Zschech, Roland Jancke, Martin Gall, André Clausner, Jens Paul, J. Warmuth, Andre Lange, K.-U. Giering, M. Otto
Publikováno v:
ESSDERC
On the example of a 28nm SRAM array, this work presents a novel reliability study which takes into account the effect of externally applied mechanical stress in circuit simulations. This method is able to predict the bit failures caused by the stress
Publikováno v:
2018 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP).
In this paper a method for dynamic fault injection and fault simulation as well as its application to MEMS based sensor systems is described. The prerequisite for this approach is the availability of accurate, but likewise numerically efficient model