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pro vyhledávání: '"Roger K. Castille"'
Autor:
S. Mullinnix, R. Simar, J. Apostol, Sanjive Agarwala, Luong Tan Nguyen, Lewis Nardini, Jerald G. Leach, Anthony M. Hill, M. Krishnan, Duc Quang Bui, Anthony J. Lell, P. Koeppen, N. Common, Timothy D. Anderson, Jeremiah E. Golston, P. Groves, P. Wiley, Raguram Damodaran, H. Mahmood, M.D. Ales, Quang-Dieu An, N.S. Nagaraj, Abhijeet Ashok Chachad, Arjun Rajagopal, Manisha Agarwala, David Hoyle, Roger K. Castille, Maria B. H. Gill
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:1532-1544
A 600-MHz VLIW digital signal processor (DSP) delivers 4800 MIPS, 2400 (16 b) or 4800 (8 b) million multiply accumulates (MMACs) at 0.3 mW/MMAC (16 b). The chip has 64M transistors and dissipates 719 mW at 600 MHz and 1.2 V, and 200 mW at 300 MHz and