Zobrazeno 1 - 10
of 112
pro vyhledávání: '"Rodrigo T. Doria"'
Autor:
Fernando O. S. Silva, Rodrigo T. Doria
Publikováno v:
Electronics Letters, Vol 60, Iss 8, Pp n/a-n/a (2024)
Abstract This work intends to investigate the impact of silicon layer thickness and substrate biasing on the UV photodetection efficiency of PIN diodes fabricated with ultra‐thin body and buried oxide (UTBB silicon‐on‐insulator [SOI]) technolog
Externí odkaz:
https://doaj.org/article/c1b43b384bac4519822ff852c2314521
Autor:
Renan Trevisoli, Marcelo A. Pavanello, Rodrigo T. Doria, Carlos E. Capovilla, Sylvain Barraud, Michelly de Souza
Publikováno v:
IEEE Transactions on Electron Devices. 69:4730-4736
Modeling Schottky Diode Rectifiers Considering the Reverse Conduction for RF Wireless Power Transfer
Autor:
Humberto Pereira da Paz, Vinicius Santana da Silva, Ivan R. S. Casella, Rodrigo T. Doria, Renan Trevisoli, Carlos Eduardo Capovilla
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:1732-1736
The aim of this work is to model Schottky diodes series rectifier for application in Radio Frequency Energy Harvesting (RFEH). A time-domain approach is proposed, including the reverse conduction of the diodes, which can significantly degrade the Pow
Publikováno v:
Journal of Integrated Circuits and Systems. 16:1-7
In this work, the electrical features related to the capacitive coupling and temperature influence of the Ultra-Thin Body and Buried Oxide SOI MOSFET (UTBB) transistors are explored through numerical simulations. The impact of the substrate bias is o
Publikováno v:
2022 36th Symposium on Microelectronics Technology (SBMICRO).
Autor:
Renan Trevisoli, Rodrigo T. Doria, Marcelo Antonio Pavanello, Sylvain Barraud, Michelly de Souza
Publikováno v:
IEEE Transactions on Nanotechnology. 20:234-242
In this work an evaluation of analog building blocks using junctionless nanowire transistors is presented. This analysis has been carried out through experimental measurements of junctionless nMOS transistors configured as two amplifier stages compos
Publikováno v:
Journal of Integrated Circuits and Systems. 8:116-124
Junctionless nanowire transistors (JNTs) are considered promising for the sub-20 nm era, since they provide a great scalability without the need for rigorously controlled doping techniques. In this work, the modeling of triple-gate JNTs is addressed,
Publikováno v:
Scopus-Elsevier
In this paper the origin of low-frequency noise in the Asymmetric Self-Cascode (A-SC) structure composed by Fully Depleted SOI nMOSFETs is investigated through experimental results. It is shown that the predominant noise source of the A-SC structure
Autor:
Antonio Cerdeira, Michelly de Souza, Rodrigo T. Doria, Marcelo Antonio Pavanello, Magali Estrada, Renan Trevisoli
Publikováno v:
Scopus-Elsevier
The linearity of Junctionless nanowire transistors operating in the linear regime has been evaluated through experimental data and numerical simulations. The influences of the fin width, the gate bias, the temperature, the doping concentration and th
Autor:
Nima Dehdashti Akhavan, Jean-Pierre Colinge, Renan Trevisoli, Isabelle Ferain, Ran Yu, Marcelo Antonio Pavanello, Rodrigo T. Doria, Ran Yan, Pedram Razavi, Michelly de Souza, Abhinav Kranti, Chi-Woo Lee
Publikováno v:
Journal of Integrated Circuits and Systems. 6:114-121
This paper performs a comparative study of the analog performance of Junctionless Nanowire Transistors (JNTs) and classical Trigate inversion mode (IM) devices focusing on the harmonic distortion. The study has been carried out in the temperature ran