Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Robin Chao"'
Publikováno v:
Advances in Mechanical Engineering, Vol 8 (2016)
A wide variety of fasteners are produced, including those for the automobile industry, household electrical appliances industry, architectural engineering, and even the aviation industry. The effects of the high-tensile bolt dephosphoring process on
Externí odkaz:
https://doaj.org/article/9c9731038ba040308420247c76671096
Autor:
Hosadurga Shobha, Tenko Yamashita, Chanro Park, Huiming Bu, R. Divakaruni, V. Basker, C. Adams, Dechao Guo, Jingyun Zhang, Lan Yu, Pietro Montanini, X.-H. Liu, A. Arceo De La Pena, Frougier Julien, Kai Zhao, Ruqiang Bao, Robert R. Robison, Nicolas Loubet, Balasubramanian S. Pranatharthi Haran, Muthumanickam Sankarapandian, Xin Miao, James Chingwei Li, Richard A. Conti, Tian Shen, Junli Wang, Praveen Joseph, Huimei Zhou, Koji Watanabe, Reinaldo A. Vega, Shanti Pancharatnam, Ruilong Xie, Curtis Durfee, A. Gaul, Daniel J. Dechene, Andrew M. Greene, Robin Chao, Dexin Kong, Heng Wu
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
In this paper, full bottom dielectric isolation (BDI) is first demonstrated on horizontally stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme vs punch through stopper (PTS) scheme has been systematically studied
Autor:
Jingyun Zhang, Nicolas Bernier, Victor Boureau, R. Coquand, O. Faynot, E. Augendre, James Chingwei Li, Nicolas Loubet, Tenko Yamashita, Raja Muthinti, Shay Reboh, Robin Chao
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
We combine advanced transmission electron microscopy (TEM) and numerical models to draw the evolution of strains over the integration of horizontally stacked Gate-All-Around Nanosheet transistors (GAANS). In particular, we measured compressive strain
Autor:
R. Divakaruni, C. Alix, Trace Hurd, M. Sankar, Aelan Mosden, Mary Breton, Thamarai S. Devarajan, Huimei Zhou, Chanemougame Daniel, Shanti Pancharatnam, Peter Biolsi, Subhadeep Kal, Andrew M. Greene, V. Basker, Kandabara Tapily, Jeffrey Smith, Balasubramanian S. Pranatharthi Haran, Jingyun Zhang, N. Haller, Michael P. Belyansky, Curtis Durfee, Robin Chao, Huiming Bu, Koji Watanabe, Xin Miao, Lan Yu, Frougier Julien, Nicolas Loubet
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
In this paper, we demonstrate a first of a kind SiGe dry etch technique for the formation of inner spacers and for channel release, enabling stacked NanoSheet (NS) gate-all-around device architectures. This novel etch involves a precisely controlled
Autor:
Jingyun Zhang, Huimei Zhou, James H. Stathis, Richard G. Southwick, Miaomiao Wang, Dechao Guo, Xin Miao, Veeraraghavan S. Basker, Huiming Bu, Robin Chao, Gauri Karve, Tenko Yamashita
Publikováno v:
IRPS
In this paper, we report the bias temperature instability (BTI) reliability in stacked gate-all-around (GAA) nanosheet (NS) devices. We show that, in addition to its superior intrinsic performance over FinFET and stacked nanowire (NW), stacked NS can
Autor:
Ali Razavieh, Bum Ki Moon, Frougier Julien, Juntao Li, Nicolas Loubet, Chen Zhang, Gen Tsutsui, Chang-Woo Sohn, Miaomiao Wang, Jingyun Zhang, Oh-seong Kwon, Xin Miao, Tenko Yamashita, Reinaldo A. Vega, Rohit Galatage, Veeraraghavan S. Basker, Robert R. Robison, Dechao Guo, Robin Chao, Chun Wing Yeung, Andrew M. Greene
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
The characteristics of Stacked Nanosheet are investigated, focusing on channel geometry. For the first time, “narrow sheet effect” on carrier transport is observed. By comparing measured electron $(\mu_{e})$ and hole $(\mu_{h})$ mobilities, and t
Autor:
Junli Wang, Hemanth Jagannathan, Takashi Ando, Tenko Yamashita, Myung-Gil Kang, Robin Chao, Jingyun Zhang, Xin Miao, Miaomiao Wang, Chen Zhang, Juntao Li, Bum Ki Moon, Ruqiang Bao, Reinaldo A. Vega, Nicolas Loubet, Zuoguang Liu, Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy, Chun Wing Yeung, Rohit Galatage, Oh-seong Kwon
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
In this paper, we report multi-threshold-voltage (multi-Vt) options for stacked Nanosheet gate-all-around (GAA) transistors. V t can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (T sus ), the combinat
Autor:
Jean Jordan-Sweet, Michael Chudzik, J. Ye, Christian Lavoie, Robin Chao, W. Wang, Charan V. V. S. Surisetty, Adra Carr, K. D. Chiu, Kuratomi Takashi, Shashank Sharma, E. Levrau, I-Cheng Chen, Raymond Hung, Avgerinos V. Gelatos, M. Stolfi, Nicolas Breil, H. Van Meer, Nicolas Loubet, Ahmet S. Ozcan
Publikováno v:
2017 Symposium on VLSI Technology.
We investigate a novel Ti Chemical Vapor Deposition (CVD Ti) technique for source/drain and trench contact silicidation. This work is a first demonstration of a highly selective, superconformal Ti process that exhibits a low p-type CVD Ti/SiGe:B cont
Autor:
Nelson Felix, Spyridon Skordas, Rohit Galatage, Junli Wang, Dinesh Gupta, Xin Miao, Deok-Hyung Lee, R. Divakaruni, John C. Arnold, Vamsi Paruchuri, Ohyun Kwon, Adra Carr, Seng Luan Lee, Soon-Cheon Seo, T. Gow, James Chingwei Li, Muthumanickam Sankarapandian, Y. Xu, Zuoguang Liu, D. Corliss, Stuart A. Sieg, Robert C. Wong, Chun Wing Yeung, Albert M. Young, Jingyun Zhang, Jeffrey C. Shearer, Huiming Bu, C. Labelle, Zhenxing Bi, Bassem Hamieh, M. Guillom, Andreas Knorr, Tenko Yamashita, Jae-Yoon Yoo, D. Brown, Peng Xu, Robin Chao, Dexin Kong, Terence B. Hook, P. Oldiges, T. Wu, Shogo Mochizuki, Young-Kwan Park, W. Xu, Raja Muthinti, S. Lian, Ruqiang Bao, S. Kanakasabapathy, Myung-Hee Na, Richard A. Conti, Frougier Julien, Robert R. Robison, Nicolas Loubet, Yann Mignot, Theodorus E. Standaert, Hemanth Jagannathan, Ho Ju Song, Pietro Montanini, Myounggon Kang, John G. Gaudiello, Mukesh Khare, Abraham Arceo, Su Chen Fan, Andrew M. Greene
Publikováno v:
2017 Symposium on VLSI Technology.
In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footpri
Autor:
Michael Shifrin, Robin Chao, Gangadhara Raja Muthinti, Matthew Sendelbach, Wei Ti Lee, Abraham Arceo de la Pena, Ronen Urenski, Susan Emans, Jacques Simon, John G. Gaudiello, Mary Breton, Aron Cepler, Yoav Etzioni
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXI.
Electrical test measurement in the back-end of line (BEOL) is crucial for wafer and die sorting as well as comparing intended process splits. Any in-line, nondestructive technique in the process flow to accurately predict these measurements can signi