Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Robert T. Golla"'
Autor:
Sebastian Turullols, Ha Pham, Yifan YangGong, Yuanjung David Lin, Hoyeol Cho, Heechoul Park, Dawei Huang, Sudesna Dash, Curtis McAllister, Hongping Penny Li, Changku Hwang, Ali Vahidsafa, Chaoyang Zheng, Vijay Srinivasan, Jeffrey S. Brooks, Francis Schumacher, Wenjay Hsu, Venkat Krishnaswamy, Georgios Konstadinidis, Alan P. Smith, Paul N. Loewenstein, Robert P. Masleid, Robert T. Golla
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:79-91
The SPARC M7 processor offers up to 3 $\times$ the throughput performance of Oracle's previous SPARC processor generation for many enterprise workloads. It contains 32 highly optimized S4 cores that include a more efficient L2 cache scheme, support f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a606e12b1bb30f7903054601615aeadb
https://doi.org/10.1109/jssc.2015.2456902
https://doi.org/10.1109/jssc.2015.2456902
Autor:
A. Smith, Curtis McAllister, Youngmoon Choi, M. Elgebaly, Jinuk Luke Shin, Hongping Li, Sebastian Turullols, Georgios Konstadinidis, Robert P. Masleid, Song Kim, M. J. Doherty, Gregory F. Grohoski, H. Sathianathan, Robert T. Golla, Heechoul Park, Sudesna Dash, M. Joshi
Publikováno v:
ISSCC
The SPARC T4 processor introduces the next generation multi-threaded 64b core to deliver up to 5x integer and 7x floating-point single-thread performance improvement over its predecessor. The chip integrates eight cores, an 8-Bank 4 MB L3 Cache, a 76
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7211f5b6f79e8c39c1bce7e99f625b48
https://doi.org/10.1109/jssc.2012.2223036
https://doi.org/10.1109/jssc.2012.2223036
Autor:
Matthew B. Smittle, G. Levinsky, Christopher H. Olson, Paul J. Jordan, M. Greenberg, Jeffrey S. Brooks, Gregory F. Grohoski, Manish K. Shah, Thomas Alan Ziaja, Mark A. Luttrell, Robert T. Golla, Jama I. Barreh, Zeid Hartuon Samoail
Publikováno v:
IEEE Micro. 32:8-19
The Sparc T4 is the next generation of Oracle's multicore, multithreaded 64-bit Sparc server processor. It delivers significant performance improvements over its predecessor, the Sparc T3 processor. The authors describe Sparc T4's key features and de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8c4679b31056147f138fda50c74326af
https://doi.org/10.1109/mm.2012.1
https://doi.org/10.1109/mm.2012.1
Autor:
Sudesna Dash, Curtis McAllister, Greg F. Grohoski, Mary Jo Doherty, Jinuk Luke Shin, Robert T. Golla, Hongping Li
Publikováno v:
2012 IEEE Asian Solid State Circuits Conference (A-SSCC).
The SPARC T4 processor introduces the next generation multi-threaded S3 core and delivers a significant single-thread performance improvement over its predecessor. The chip integrates eight S3 cores, an 8-Bank 4MB L3 Cache, a 768GB/sec crossbar, a me
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::813ee906963ca0dc03a6c3eac24fef7a
https://doi.org/10.1109/ipec.2012.6522613
https://doi.org/10.1109/ipec.2012.6522613
Autor:
Robert T. Golla, Paul J. Jordan
Publikováno v:
2011 IEEE Hot Chips 23 Symposium (HCS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d39669a72479ce5f1a269b2452e0827f
https://doi.org/10.1109/hotchips.2011.7477506
https://doi.org/10.1109/hotchips.2011.7477506
Publikováno v:
Integrated Circuits and Systems ISBN: 9781441902627
Multicore Processors and Systems
Multicore Processors and Systems
Many important commercial server applications are throughput-oriented. Chip multiprocessors (CMPs) are ideally suited to handle these workloads, as the multiple processors on the chip can independently service incoming requests. To date, most CMPs ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff2e4c7d05f36c93349d5603fcedda94
https://doi.org/10.1007/978-1-4419-0263-4_7
https://doi.org/10.1007/978-1-4419-0263-4_7
Autor:
D. Sheahan, A. Wynn, Jeffrey S. Brooks, Lawrence Spracklen, Robert T. Golla, Nils Gura, J. Barren, Ricky C. Hetherington, Paul J. Jordan, Gregory F. Grohoski, Christopher H. Olson, Manish K. Shah, Mark A. Luttrell, B. Sana
Publikováno v:
2007 IEEE Asian Solid-State Circuits Conference.
UltraSPARC T2 is Sun Microsystems' second generation multi-core, multi-threaded SPARC System-on-a-chip. It delivers twice the throughput performance of the first generation UltraSPARC T1 processor in essentially the same power envelope. UltraSPARC T2
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ce968e0834a80cea67c89d320ccbb13
https://doi.org/10.1109/asscc.2007.4425786
https://doi.org/10.1109/asscc.2007.4425786