Výsledky vyhledávání - "Robert S. Chau"

Process and Packaging Innovations for Moore’s Law Continuation and Beyond

Autor: Robert S. Chau

Publikováno v: 2019 IEEE International Electron Devices Meeting (IEDM).

This presentation describes various revolutionary process and packaging technologies on the horizon that will (i) extend Moore’s Law scaling through and beyond the next decade and (ii) enable many new, exciting integrated circuit opportunities and

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3279a7ed52c655db66a1eb422efc348c
https://doi.org/10.1109/iedm19573.2019.8993462

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Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology

Autor: Matthew V. Metz, Robert S. Chau, B. Jin, Marko Radosavljevic, Brian S. Doyle, Gilbert Dewey, Amlan Majumdar, Mark L. Doczy, Suman Datta, Justin K. Brask, Jack T. Kavalieros

Publikováno v: Microelectronic Engineering. 80:1-6

High-k gate dielectrics and metal gate electrodes are required for enabling continued equivalent gate oxide thickness scaling, and hence high performance, and for controlling gate oxide leakage for both future silicon and emerging nonsilicon nanoelec

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f8f3f0a36c04450010b97c608b4f417a
https://doi.org/10.1016/j.mee.2005.04.035

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Silicon nano-transistors for logic applications

Autor: Scott Hareland, Brian S. Doyle, Jack T. Kavalieros, Matthew V. Metz, Suman Datta, Mark L. Doczy, B. Jin, Boyan Boyanov, Robert S. Chau

Publikováno v: Physica E: Low-dimensional Systems and Nanostructures. 19:1-5

Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET de

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b3c24554e36c25b663c596d4d7e0370d
https://doi.org/10.1016/s1386-9477(03)00284-4

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Surface Preparation and Passivation of III-V Substrates for Future Ultra-High Speed, Low Power Logic Applications

Autor: Marko Radosavljevic, Willy Rachmady, Robert S. Chau, Mantu K. Hudait, James M. Blackwell, Gilbert Dewey, Robert B. Turkot

Publikováno v: Solid State Phenomena. :165-167

III-V compound semiconductors have been recognized among the potential options for continuing transistor power-performance scaling owing to their ultra high charge carrier mobility. In order to realize their potential in high performance and lower-po

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a964a5ee5b8d108d6d8e1299e6644600
https://doi.org/10.4028/www.scientific.net/ssp.145-146.165

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Integrated nanoelectronics for the future

Autor: Jack T. Kavalieros, Brian S. Doyle, Robert S. Chau, Suman Datta, Kevin Zhang

Publikováno v: Nature Materials. 6:810-812

Integrated electronics has come a long way since the invention of the transistor in 1947 and the fabrication of the first integrated circuit in 1958. Given feature sizes as small as a few nanometres, what will the future hold for integrated electroni

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ba81444d2ecac381d8e496a2362ab4fb
https://doi.org/10.1038/nmat2014

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The ultimate CMOS device and beyond

Autor: Ravi Pramod Vedula, Annalisa Cappellani, Kelin J. Kuhn, Uygar E. Avci, Roza Kotlyar, Robert S. Chau, Seiyon Kim, Marko Radosavljevic, Ian A. Young, Sasikanth Manipatruni, Martin D. Giles, Rafael Rios, Sadasivan Shankar, Dmitri E. Nikonov, Chytra Pawashe, Michael Haverty

Publikováno v: 2012 International Electron Devices Meeting.

For the past 40 years, relentless focus on Moore's Law transistor scaling has delivered ever-improving CMOS transistor density. This paper discusses architectural and materials options which will contribute to the ultimate CMOS device. In addition, t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::50afdf3a968285a8ce5ed038769c6f55
https://doi.org/10.1109/iedm.2012.6479001

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Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

Publikováno v: 2011 International Electron Devices Meeting.

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (L SIDE ) have been fabricated and compared. For the first time, 3-D Tri-g

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::32bdc6d1de06cd81e40356570b6b746d
https://doi.org/10.1109/iedm.2011.6131661

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Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

Autor: Matthew V. Metz, G. Dewey, Roza Kotlyar, L. Pan, Jack Portland Kavalieros, Uday Shah, W. K. Liu, W. Rachmady, R. Pillarisetty, Niloy Mukherjee, D. Lubyshev, Robert S. Chau, Benjamin Chu-Kung, K. Millard, J. M. Fastenau, Marko Radosavljevic

Publikováno v: 2010 International Electron Devices Meeting.

In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (L SIDE ) of 5nm are reported for the first time. The high-K gate die

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::43f8829683a26962416613f2ce210b29
https://doi.org/10.1109/iedm.2010.5703306

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Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications

Autor: Robert S. Chau, S. Corcoran, W. Rachmady, Benjamin Chu-Kung, Matthew V. Metz, K. Millard, W. K. Liu, D. Lubyshev, G. Dewey, J. M. Fastenau, Marko Radosavljevic, Mantu K. Hudait, Uday Shah, Niloy Mukherjee, Jack Portland Kavalieros

Publikováno v: 2009 IEEE International Electron Devices Meeting (IEDM).

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO x -2nm InP) in the In 0.7 Ga 0.3 As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::647d2226b18c0b361e6680e7f6990781
https://doi.org/10.1109/iedm.2009.5424361

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