Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Robert Rogenmoser"'
Autor:
Lawrence T. Clark, Robert Rogenmoser
Publikováno v:
IEEE Micro. 33:18-26
CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::350f4880acfb13ccbee7f7d55b2bc847
https://doi.org/10.1109/mm.2013.10
https://doi.org/10.1109/mm.2013.10
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 11:490-500
A unique LVS (layout-versus-schematic) methodology has been developed for the verification of a four-core microprocessor with multiple power domains using a triple-well 90-nm CMOS technology. The chip is migrated from its previous generation that is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92bb83c9b2c543a17cd0e841226fa27a
https://doi.org/10.1145/1142155.1142166
https://doi.org/10.1145/1142155.1142166
Autor:
G. Yiu, M. Pearce, Daniel C. Murray, Robert Rogenmoser, Dongwook Suh, Zongjian Chen, S. Nishimoto, D. Rodriguez, V. von Kaenel, E. Supnet, M. Oyker
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:1857-1865
The load/store pipe for a low-power 1-GHz embedded processor is described. For area savings and logic complexity reduction, the load/store pipe is clocked at twice the frequency of the processor core. It can sustain two load or store operations per c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa174e9c105904d3d6f041efcc9ed15d
https://doi.org/10.1109/jssc.2003.818296
https://doi.org/10.1109/jssc.2003.818296
Autor:
M. Wojko, G. Krishnan, Vineet Agrawal, Mitsuaki Hori, S. Wakayama, Samuel Leshner, T. Yamada, Taiji Ema, J. Mitani, D. Zhao, T. Bakishev, Lawrence T. Clark, T. Tsuruta, S. Moriwaki, N. Kepler, Robert Rogenmoser, Pushkar Ranade, R. Roy, David A. Kidd
Publikováno v:
CICC
An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MH
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ae5d005e7c95e4a8f30092988a6d760
https://doi.org/10.1109/cicc.2013.6658514
https://doi.org/10.1109/cicc.2013.6658514
Publikováno v:
CICC
A process monitor based on slew-rate measurement has been applied to a body bias control system to detect the process corners and adjust the body bias voltage necessary to meet the power and performance requirements for CMOS circuits. The process mon
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c87525a045984f4023cf040bc266f94
https://doi.org/10.1109/cicc.2013.6658516
https://doi.org/10.1109/cicc.2013.6658516
Autor:
Robert Rogenmoser
Publikováno v:
2012 IEEE Hot Chips 24 Symposium (HCS).
This article consists of a collection of slides from the author's conference presentation on the ability to reduce transistor variability for high performance, low power chips. Some of the specific topics discussed include: transistor variability and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a97c24ffa2e8e79bad37c12eee196725
https://doi.org/10.1109/hotchips.2012.7476495
https://doi.org/10.1109/hotchips.2012.7476495
Autor:
G. Yiu, D. Murrray, D. Rodriguez, Dongwook Suh, Zongjian Chen, E. Supnet, M. Pearce, Robert Rogenmoser, S. Nishinnoto, M. Oyker
Publikováno v:
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dbabe7c5459206ad9a1e317d041aa3df
https://doi.org/10.1109/isscc.2003.1234325
https://doi.org/10.1109/isscc.2003.1234325
Autor:
L. O'Donnell, V. Sundaresan, Brian J. Campbell, Tuan Do, G. Yee, R. Blake, Donald A. Priore, N. Bunger, Daniel C. Murray, E. Supnet, D. Kidd, Ingino Joseph M, D. Rodriguez, M. Pearce, G. Yiu, Sribalan Santhanam, Jong Lee, M. Carlson, K. Anne, V. von Kaenel, J. Cheng, C. Vo, Robert Rogenmoser, S. Nishimoto, R. Wen, Dongwook Suh, Zongjian Chen, David A. Kruckemyer, M. Panich, Daniel W. Dobberpuhl, M. Oykher, R. Allmon
Publikováno v:
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).
The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3ecd1e71f24d74a85e5bf3a4ddc378b
https://doi.org/10.1109/vlsic.2001.934209
https://doi.org/10.1109/vlsic.2001.934209
Publikováno v:
Parallel Problem Solving from Nature — PPSN IV ISBN: 9783540617235
PPSN
PPSN
The performance of a CMOS circuit depends heavily on its transistor sizes. We have tested a standard optimizer, a Monte Carlo scheme and a method based on Genetic Algorithms combined with very accurate SPICE simulations to automatically optimize tran
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::069ba3d730377fb90ce739d740434167
https://doi.org/10.1007/3-540-61723-x_1048
https://doi.org/10.1007/3-540-61723-x_1048
Conference
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