Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Robert P. Masleid"'
Autor:
Sebastian Turullols, Ha Pham, Yifan YangGong, Yuanjung David Lin, Hoyeol Cho, Heechoul Park, Dawei Huang, Sudesna Dash, Curtis McAllister, Hongping Penny Li, Changku Hwang, Ali Vahidsafa, Chaoyang Zheng, Vijay Srinivasan, Jeffrey S. Brooks, Francis Schumacher, Wenjay Hsu, Venkat Krishnaswamy, Georgios Konstadinidis, Alan P. Smith, Paul N. Loewenstein, Robert P. Masleid, Robert T. Golla
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:79-91
The SPARC M7 processor offers up to 3 $\times$ the throughput performance of Oracle's previous SPARC processor generation for many enterprise workloads. It contains 32 highly optimized S4 cores that include a more efficient L2 cache scheme, support f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a606e12b1bb30f7903054601615aeadb
https://doi.org/10.1109/jssc.2015.2456902
https://doi.org/10.1109/jssc.2015.2456902
Autor:
King C. Yen, Aparna Ramachandran, Timothy P. Johnson, Yongning Sheng, Jason M. Hart, Daisy Jian, Rakesh Mehta, Yuefei Ge, Dawei Huang, Lance Kwong, Hoyeol Cho, Zuxu Qin, Changku Hwang, Jinuk Luke Shin, Umesh Gajanan Nawathe, Robert P. Masleid, Venkat Krishnaswamy, Georgios Konstadinidis, Hari Sathianathan, Gregory Gruber, Sebastian Turullols
Publikováno v:
ISSCC
The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9a65bf3aeb8482508a1512e9ba2b864
https://doi.org/10.1109/jssc.2013.2284648
https://doi.org/10.1109/jssc.2013.2284648
Autor:
A. Smith, Curtis McAllister, Youngmoon Choi, M. Elgebaly, Jinuk Luke Shin, Hongping Li, Sebastian Turullols, Georgios Konstadinidis, Robert P. Masleid, Song Kim, M. J. Doherty, Gregory F. Grohoski, H. Sathianathan, Robert T. Golla, Heechoul Park, Sudesna Dash, M. Joshi
Publikováno v:
ISSCC
The SPARC T4 processor introduces the next generation multi-threaded 64b core to deliver up to 5x integer and 7x floating-point single-thread performance improvement over its predecessor. The chip integrates eight cores, an 8-Bank 4 MB L3 Cache, a 76
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7211f5b6f79e8c39c1bce7e99f625b48
https://doi.org/10.1109/jssc.2012.2223036
https://doi.org/10.1109/jssc.2012.2223036
Autor:
Changku Hwang, Paul N. Loewenstein, Penny Li, Hoyeol Cho, Heechoul Park, Sudesna Dash, Francis Schumacher, Jinuk Luke Shin, Yuanjung David Lin, Wenjay Hsu, Venkat Krishnaswamy, Georgios Konstadinidis, Robert P. Masleid, Chaoyang Zheng, Curtis McAllister, Vijay Srinivasan, Dawei Huang
Publikováno v:
ISSCC
The SPARC M7 processor delivers more than 3x throughput performance improvement over its predecessor SPARC M6 for commercial applications. It introduces new design features, such as the S4 core, a 64MB L3 cache subsystem with application data integri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::505a30dca4209b053f118f6ef3ee62f4
https://doi.org/10.1109/isscc.2015.7062931
https://doi.org/10.1109/isscc.2015.7062931
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.