Zobrazeno 1 - 10
of 38
pro vyhledávání: '"Robert H. Havemann"'
Autor:
Girish A. Dixit, Robert H. Havemann
Publikováno v:
Handbook of Semiconductor Manufacturing Technology ISBN: 9781315213934
This chapter provides an overview of copper and low-k interconnect integration including process architectures, materials, performance, and reliability issues as well as future scaling challenges and potential technology directions. The simultaneous
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b80bd3b5ddd38eefe6ed310d0a34de4c
https://doi.org/10.1201/9781420017663-2
https://doi.org/10.1201/9781420017663-2
Autor:
Hideki Matsuhashi, Volker A. Blaschke, Ki-Don Lee, Robert H. Havemann, Paul S. Ho, E.T. Ogawa
Publikováno v:
Journal of Electronic Materials. 31:1052-1058
Recent results on up-direction electromigration (EM) studies on Cu dual-damascene (DD) interconnects are presented. The issue of the DD process and its potential effect on EM reliability is described with special focus on the peculiarities of the DD
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::134b3878ecb6c5db95ec00a3d221b3eb
https://doi.org/10.1007/s11664-002-0042-6
https://doi.org/10.1007/s11664-002-0042-6
Publikováno v:
Thin Solid Films. 320:52-57
We have successfully integrated Al plugs into a 0.25- μ m CMOS flow using two different chemical vapor deposition (CVD) Al metallization process schemes. Both process schemes utilized CVD Al grown from dimethyl aluminum hydride (DMAH) followed by ph
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb1e713365992da55b5afc124ed75633
https://doi.org/10.1016/s0040-6090(97)01064-x
https://doi.org/10.1016/s0040-6090(97)01064-x
Autor:
Q. Z. Hong, P.J Chen, Lissa K. Magel, Jiong-Ping Lu, H. L. Tsai, Girish A. Dixit, Joseph D. Luttmer, Robert H. Havemann, Wei-Yung Hsu
Publikováno v:
Thin Solid Films. 320:20-25
The thermal stability of Al–0.5% Cu/barrier/TiSi x multilayer structures is investigated. The barriers studied in this work are TiN films prepared by physical vapor deposition (PVD) and TiN-based barrier films prepared by metal–organic chemical v
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::877a245a50821a56ace8e82a94453a40
https://doi.org/10.1016/s0040-6090(97)01060-2
https://doi.org/10.1016/s0040-6090(97)01060-2
Autor:
Yu-Pei Chen, Joseph D. Luttmer, Wei-Yung Hsu, Jiong-Ping Lu, Anthony J. Konecni, Girish A. Dixit, Robert H. Havemann
Publikováno v:
Thin Solid Films. 320:73-76
New contact fill integration schemes were developed for high aspect ratio Gb DRAM contact metallization. Integration schemes for both tungsten-plug contacts and aluminum-plug contacts were studied. For tungsten-plug contacts, various types of titaniu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d3e824b17680f11beaee353f74bca7b
https://doi.org/10.1016/s0040-6090(97)01068-7
https://doi.org/10.1016/s0040-6090(97)01068-7
Autor:
Alexander J. Bierwag, Paul S. Ho, A. N. Ramamurthi, V. Blaschke, Mark R. Breen, Ennis T. Ogawa, Ki Don Lee, Robert H. Havemann, Patrick R. Justison, Anne Nelsen, Hideki Matsuhashi, David Griffiths
Publikováno v:
Applied Physics Letters. 78:2652-2654
Electromigration results have provided clear evidence of a short or “Blech” length effect in dual- damascene, Cu/oxide, multilinked interconnects. The test structure incorporates a repeated chain of Blech-type line elements and is amenable to fai
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::59f301ed83feb32f960ffa70f8a56331
https://doi.org/10.1063/1.1365414
https://doi.org/10.1063/1.1365414
Autor:
Q. Z. Hong, J. D. Luttmer, L. K. Magel, Wei-Yung Hsu, Robert H. Havemann, Jiong-Ping Lu, Girish A. Dixit
Publikováno v:
ChemInform. 28
A new process for preparing TiN-based barrier films is reported. The process consists of thermal decomposition of a metallorganic precursor, tetrakis(dimethylamino)-titanium, followed by postdeposition annealing in silane ambient. Thin films fabricat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92149d209977c958000af9cb1165a001
https://doi.org/10.1002/chin.199714221
https://doi.org/10.1002/chin.199714221
Autor:
Kelly Taylor, Hung‐Yu Liu, Monte A. Douglas, Joseph D. Luttmer, Wei-Yung Hsu, Qi‐Zhong Hong, Robert H. Havemann, Lissa K. Magel
Publikováno v:
Journal of The Electrochemical Society. 144:L248-L250
The effects of Ar sputter etch and Ti deposition temperature on the crystalline orientation of Ti films deposited by long-throw sputtering geometry are reported. Both Ar sputter etch and high Ti deposition temperature degraded the Ti microstructure f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bed86394ca09719094fffb4d10b0eb80
https://doi.org/10.1149/1.1837933
https://doi.org/10.1149/1.1837933
Autor:
Roger A. Haken, N. Iyengar, Robert H. Eklund, David B. Scott, Che-Chia Wei, Robert H. Havemann, K. Fung, Mark S. Rodder, Hiep V. Tran, Richard A. Chapman, David A. Bell, R. Fleck, D. Le, M.G. Harward, T. Suzuki
Publikováno v:
IEEE International Solid-State Circuits Conference.
A 1-Mb*1 BiCMOS ECL (emitter-coupled-logic) I/O SRAM (static random access memory) is fabricated using a 0.8- mu m BiCMOS process. This memory device utilizes a 76- mu m/sup 2/ full-CMOS six-transistor memory cell, a dual-MOS current-source BiCMOS bi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::227acb96af7d7cf076d6d0049b111159
https://doi.org/10.1109/isscc.1989.48223
https://doi.org/10.1109/isscc.1989.48223
Autor:
J. Graham, Hiep V. Tran, T. Suzuki, Roger A. Haken, C. Blanton, Che-Chia Wei, Robert H. Eklund, Richard A. Chapman, Mark S. Rodder, Robert H. Havemann, R. Sundaresan, V. Rao, David B. Scott, Thomas C. Holloway, H. Terazawa
Publikováno v:
International Technical Digest on Electron Devices Meeting.
The authors describe a 0.5- mu m BiCMOS technology for high-performance logic and SRAMs (static RAMs) which is capable of supporting 5-V hot-carrier-hard circuit designs. In these designs the maximum drain-to-source voltage across a 0.5- mu m NMOS de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b83bfbe84552b90bbcb0e5cb34122e70
https://doi.org/10.1109/iedm.1989.74313
https://doi.org/10.1109/iedm.1989.74313