Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Robert E. Busch"'
Autor:
Mark D. Jacunski, P. K. Lane, Michael A. Roberge, Dale E. Pontius, S. Sliva, John A. Fifield, Robert E. Busch, Adrian J. Paparelli, Darren L. Anand, Gary Pomichter, Matthew C. Lanahan
Publikováno v:
CICC
A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V DD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14d31cabf0d4ccfd61c6807436dc9d6c
https://doi.org/10.1109/cicc.2010.5617634
https://doi.org/10.1109/cicc.2010.5617634
Autor:
D. Morency, M. Bus, Robert E. Busch, J. Kosson, R. Newhart, J. Morrish, R. Parent, T. Redman, M. Clinton, D. Plouffe, C. Kilmer, E. Thoma, D. Tewarson, T. Bronson
Publikováno v:
1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
A 4Mb CMOS DRAM organized 1Mb×4, measuring 6.35mm × 12.3mm, and operating at a typical row access time of 65ns, will be described. The design utilizes a double buffer architecture to achieve a static column access time of 25ns. Half V dd -folded bi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::34551c2e1d4311705321fc3fa67419bc
https://doi.org/10.1109/isscc.1987.1157207
https://doi.org/10.1109/isscc.1987.1157207
Autor:
Glenn Peter Giacalone, S. Divakaruni, Peter Joel Jenkins, John A. Fifield, M. Hodges, Jeffrey S. Zimmerman, Robert E. Busch, A. Davidovich, M. Vincent, M. Kozyrczak, Christopher P. Miller, Wayne J. Howell, C. Reed, F. Creed, Thomas E. Obremski, Charles Edward Drake, T. von Reyn, G. Rohrbaugh, C. Ematrudo
Publikováno v:
1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.
Several cache-DRAMs have been reported, but all require multiple chips to implement an L2 cache system. The advent of 20 ns, 16 Mb DRAM technology has made a high-speed single-chip 1MB cache possible, replacing multiple SRAM and logic modules, saving
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc4f3df86c68ee4b283ada19fb890d82
https://doi.org/10.1109/isscc.1996.488721
https://doi.org/10.1109/isscc.1996.488721
Publikováno v:
ITC
Process scaling and the need for smaller SRAM cells challenges process technologies to make millions of robust and reliable bitline contacts on a single chip. Another challenge is to identify marginal, resistive and unreliable bitline contacts given
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d9e73261e84ddb98703af0ff1fcde95
https://doi.org/10.1109/test.2001.966699
https://doi.org/10.1109/test.2001.966699