Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Robert C. Wong"'
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIII.
At the early stage of a new technology development, Ground Rule (GR) calculations are performed assuming design targets are met, and all the process variations are within certain process assumptions. However, as technology matures, it is expensive, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3661554f1d25779ba7c8c3cca0413aa0
https://doi.org/10.1117/12.2515636
https://doi.org/10.1117/12.2515636
Autor:
David Clark, Carl Schiller, Stephen Lucarini, Ishtiaq Ahsan, Fred J. Towler, Zhigang Song, Robert C. Wong, Felix Beaudoin
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 28:474-479
The SRAM bitcell array has been traditionally used as a yield learning vehicle for new technologies. However, the yield of the SRAM bitcell is susceptible to parametric variations and subtle process defects/variations. In this paper, a new functional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f696121311a8e234ef63a4da60c55562
https://doi.org/10.1109/tsm.2015.2487267
https://doi.org/10.1109/tsm.2015.2487267
Autor:
Terence B. Hook, Matthew M. Ziegler, Keunwoo Kim, Phil Oldiges, Sudesh Saroop, Carl J. Radens, Chun-Chen Yeh, Robert C. Wong, Rajiv V. Joshi, Pranita Kerber, Ajay N. Bhoj, Rouwaida Kanj
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:534-543
We propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5aadd458f2eb49b62f4337eae3f083f4
https://doi.org/10.1109/tvlsi.2014.2313815
https://doi.org/10.1109/tvlsi.2014.2313815
Autor:
Nelson Felix, Spyridon Skordas, Rohit Galatage, Junli Wang, Dinesh Gupta, Xin Miao, Deok-Hyung Lee, R. Divakaruni, John C. Arnold, Vamsi Paruchuri, Ohyun Kwon, Adra Carr, Seng Luan Lee, Soon-Cheon Seo, T. Gow, James Chingwei Li, Muthumanickam Sankarapandian, Y. Xu, Zuoguang Liu, D. Corliss, Stuart A. Sieg, Robert C. Wong, Chun Wing Yeung, Albert M. Young, Jingyun Zhang, Jeffrey C. Shearer, Huiming Bu, C. Labelle, Zhenxing Bi, Bassem Hamieh, M. Guillom, Andreas Knorr, Tenko Yamashita, Jae-Yoon Yoo, D. Brown, Peng Xu, Robin Chao, Dexin Kong, Terence B. Hook, P. Oldiges, T. Wu, Shogo Mochizuki, Young-Kwan Park, W. Xu, Raja Muthinti, S. Lian, Ruqiang Bao, S. Kanakasabapathy, Myung-Hee Na, Richard A. Conti, Frougier Julien, Robert R. Robison, Nicolas Loubet, Yann Mignot, Theodorus E. Standaert, Hemanth Jagannathan, Ho Ju Song, Pietro Montanini, Myounggon Kang, John G. Gaudiello, Mukesh Khare, Abraham Arceo, Su Chen Fan, Andrew M. Greene
Publikováno v:
2017 Symposium on VLSI Technology.
In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footpri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8172c77d8489643bbaac20dc37532850
https://doi.org/10.23919/vlsit.2017.7998183
https://doi.org/10.23919/vlsit.2017.7998183
Publikováno v:
2017 IEEE International Interconnect Technology Conference (IITC).
While BEOL process/integration stride to explore new technologies to support scaling needs, BEOL design rules are hindering design scaling due to the increasing process complexity. A design rule calculation tool that can consider all relevant process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06c4908754d9799b5c721d54657b2059
https://doi.org/10.1109/iitc-amc.2017.7968938
https://doi.org/10.1109/iitc-amc.2017.7968938
Publikováno v:
SPIE Proceedings.
Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2174a808ee48905f5dc9fe2859da5cc5
https://doi.org/10.1117/12.2218636
https://doi.org/10.1117/12.2218636
Autor:
Carl Schiller, Fred J. Towler, Zhigang Song, Robert C. Wong, Ishtiaq Ahsan, Felix Beaudoin, David Clark
Publikováno v:
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
The SRAM bitcell array has been traditionally used as a yield learning vehicle for new technologies. However, the yield of the SRAM bitcell is susceptible to parametric variations and subtle process defects/ variations. In this work a new functional
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7f71308bbc970d650dbb7db6b715fd1
https://doi.org/10.1109/asmc.2014.6846946
https://doi.org/10.1109/asmc.2014.6846946
Autor:
Robert C. Wong
Publikováno v:
Integrated Circuits and Systems ISBN: 9781441966056
SRAM has been generally characterized with some SNM [12] from the voltage–voltage (VV) plots or the Icrit from the current–voltage (IV) plots. They do indicate the robustness of the SRAM operations but would not provide sufficient information for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15818303867c1d2bd92a0aaa6bdc8c39
https://doi.org/10.1007/978-1-4419-6606-3_5
https://doi.org/10.1007/978-1-4419-6606-3_5
Autor:
J. Pape, Nam-Sung Kim, Martin Ostermayr, Deleep R. Nair, Melanie J. Sherony, Craig S. Lage, Jaeger Daniel, Franck Arnaud, Y. Gao, Deok-Hyung Lee, H.S. Yang, C. Schiller, X. Chen, S. Stiffler, An L. Steegen, Kenneth J. Stein, J. Sudijono, Christopher V. Baiocco, Haoren Zhuang, Robert C. Wong, Y. Takasu, Ho-Kyu Kang, Sayeed A. Badrudduza, J. Wallner, Laegu Kang, James Chingwei Li, Aaron Thean, Y.W. Teh, L. Zhuang, R. Hasumi, S. Samavedam, D.P. Sun, Mukesh Khare
Publikováno v:
2008 IEEE International Electron Devices Meeting.
This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, tha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bcc347a597544ead57bce41996b65ef0
https://doi.org/10.1109/iedm.2008.4796660
https://doi.org/10.1109/iedm.2008.4796660
Autor:
J. Toomey, D. Hoyniak, Randy W. Mann, D. Lea, M. Weybright, C. Wann, Yoo-Mi Lee, Shang-Bin Ko, Robert C. Wong, P. Croce, David J. Frank, J. Sudijono
Publikováno v:
IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..
SRAM stability during word line disturb (access disturb) is becoming a key constraint for V/sub DD/ scaling (Burnett, 1994). In this paper we present a design methodology for SRAM stability during access disturb. In this methodology, the SRAM access
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::56fb8d516c6b82aa9b3fc45214f8e21e
https://doi.org/10.1109/vtsa.2005.1497065
https://doi.org/10.1109/vtsa.2005.1497065