Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Rico Backasch"'
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 18:1-26
Multicore System-on-Chip (SoC) implementations of embedded systems are becoming very popular. In these systems it is possible to spread out computations over many cores. On one hand this leads to better energy efficiency if clock frequencies and core
Autor:
Jan Moritz Joseph, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Rico Backasch, Christopher Blochwitz, Sven Groppe
Publikováno v:
ReConFig
In this paper, a data structure and a hardware acceleration for dictionary generation for Semantic Web databases are presented. Current hardware accelerators for databases are based on co-processor designs supporting software-centric applications: on
Autor:
Christopher Blochwitz, Stefan Werner, Thilo Pionteck, Gerald Hempel, Rico Backasch, Sven Groppe
Publikováno v:
ReConFig
This paper presents a generic hardware design which allows the composition of application specific datapaths at runtime. The architectural template consists of a grid of identical tiles which are connected by a lightweight network-onchip. A processor
Autor:
Jannik Piper, Christopher Blochwitz, Stefan Werner, Sven Groppe, Thilo Pionteck, Rico Backasch, Dennis Heinrich
Publikováno v:
ReCoSoC
In this paper, we present the fully automated composition and execution of Semantic Web queries within a hardware/software system which uses a Field Programmable Gate Array (FPGA) as an accelerator. The presented approach allows to write a query in t
Publikováno v:
ReConFig
Relocation of partial bitstreams is in the focus of researchers for many years. Several design flows for module relocations have been proposed in the past. In general, these design flows start with a manual identification of equally sized and structu
Publikováno v:
CIT
In this paper, we investigate the use of Field Programmable Gate Arrays (FPGAs) to enhance the performance of filter expressions in Semantic Web databases. The filter operator is a central part of query evaluation. Its main objective is to reduce the
Autor:
Christian Hochberger, Rico Backasch
Publikováno v:
Architecture of Computing Systems – ARCS 2013 ISBN: 9783642364235
ARCS
ARCS
Reconfigurable architectures combine the high flexibility of general purpose processors with the high performance of specialized hardware architectures. They can be implemented on field programmable gate arrays or on custom coarse grain reconfigurabl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b81e4bfedf0b222c9cf27e0f5f8dcdf9
https://doi.org/10.1007/978-3-642-36424-2_16
https://doi.org/10.1007/978-3-642-36424-2_16