Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Richard J. Luebs"'
Publikováno v:
ICCD
A low cost, high performance implementation of Hewlett-Packard's PA-RISC 1.1 architecture is described. This chipset is used in HP's 9000 series 700 workstations. The processor consists of two VLSI chips, a CPU and a floating point coprocessor, which
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::570b0c98a5626016a909f37cf3e05a07
https://doi.org/10.1109/iccd.1991.139900
https://doi.org/10.1109/iccd.1991.139900
Autor:
Michael A Buckley, Craig A. Gleason, D. Hollenbeck, Richard J. Luebs, K. Erskine, Joel D. Lamb, B. Long, J. Wheeler, S. McMullen, J. Yetter, C. Kohlhardt, H. Hill, Daniel L Halperin, Jonathan P Lotz, Robert J. Horning, Patrick Knebel, R. Novak, Darius Tanksalvala, H. Tran, L. Sigel, C. Simpson, Doug Quarnstrom, Donald Kipp, John R. Spencer, S. Chapin, Eric Delano, Duncan Weir, E. Rashid, Thomas R. Hotchkiss, M. Forsyth, T. Gaddis
Publikováno v:
1990 37th IEEE International Conference on Solid-State Circuits.
A CMOS CPU which operates at 90 MHz under typical conditions and implements an existing RISC (reduced-instruction-set-computer) 140-instruction set is described. The processor has been designed for sustained performance for workstation and both comme
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a72489e0852fc0c8239643d7019fe6b
https://doi.org/10.1109/isscc.1990.110125
https://doi.org/10.1109/isscc.1990.110125