Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Ri-hui Sun"'
Autor:
Yi Yang, Xuan-Jie Liu, Peng He, Xiao-Jun Chen, Ri-hui Sun, Paul-Chang Lin, Jian-Yong Jiang, Guang-Ning Li
Publikováno v:
ECS Transactions. 52:443-451
TSV (Through Silicon Via) is a new method for 3D technology (IC integration). Different chips can be connected with the Cu line through silicon substrate. Via area is so deep (usually 100-300um) that we need thicker barrier and seed layer. The Cu pla
Publikováno v:
ECS Transactions. 44:737-743
Hillock is formed at the film surface in Cu metallization process. During the growth of hillock, the tensile stress built in the copper (Cu) metal film due to the relieved thermal expansion coefficients. These "hillocks" are just areas of localized c
Publikováno v:
ECS Transactions. 44:745-749
Via bottom void is one of the problems related to the metal interconnections in semiconductor devices. In 0.13μm technology, Novellus Sabre serial is wildly applied as copper(Cu) electro chemical plating (ECP) tool, but the problem of high hit ratio
Autor:
Ri-Hui Sun, Charles Xing, Yi Yang, Paul-Chang Lin, Xiao-Chun Kang, Dong-Yi Zhou, Jian-Yong Jiang, Peng He
Publikováno v:
ECS Transactions. 44:797-801
Copper (Cu) material is being widely used in the advance ultra large-scale integration (ULSI) in the metallization process due to its low resistivity and good performance on EM in 130nm and below technology node. In Cu metallization process of 130nm,
Autor:
Paul-Chang Lin, Ji-Wei Zhang, Ri-Hui Sun, Cheng Xing, Jian-Yong Jiang, Xiao Li, Hua Zhou, Yi-Jun Bian
Publikováno v:
ECS Transactions. 18:677-680
In copper metallization of BEOL, ECP is used for copper deposition in via or trench for interconnection after PVD barrier & seed process. But ECP film easily suffers pits defect with swirl pattern that is a killer defect to CP yield. This paper intro