Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Rene Krenz-Baath"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35:2104-2117
Test compaction is an important aspect in the post-production test since it is able to reduce the test data and the test costs, respectively. Current automatic test pattern generation (ATPG) methods treat all faults independently from each other whic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4449702fbd0aeb580e4b05136588f53b
https://doi.org/10.1109/tcad.2016.2552822
https://doi.org/10.1109/tcad.2016.2552822
Publikováno v:
ITC
IEEE 1687 enables flexible access to on-chip instruments via dynamically reconfigurable networks. Reconfiguration allows reducing instrument access time by keeping only those instruments on the scan-path which are required for each access. To perform
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c6e26c65f0b806a4224c62009a5f7c5
https://doi.org/10.1109/test.2016.7805838
https://doi.org/10.1109/test.2016.7805838
Publikováno v:
SIES
Multi-cluster systems with time-triggered networks are suitable for large safety-critical systems, which benefit from the inherent fault isolation and temporal predictability of the time-triggered paradigm. These networks depend on communication sche
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee6320931f2c82e7b84ac46d815d891f
https://doi.org/10.1109/sies.2016.7509415
https://doi.org/10.1109/sies.2016.7509415
Publikováno v:
SIES
Many embedded systems are deployed with multi-core platforms where processor cores are interconnected by networks-on-a-chip. Time-triggered networks-on-a-chip are ideal for safety-critical systems due to the inherent fault isolation and temporal pred
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f63cb58c10649be18269e80b93614638
https://doi.org/10.1109/sies.2015.7185054
https://doi.org/10.1109/sies.2015.7185054
Publikováno v:
ITC
IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, powe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5238500d192fc0a592d03c77af12b42b
https://lup.lub.lu.se/record/8055367
https://lup.lub.lu.se/record/8055367
Publikováno v:
ETS
Test compaction is an important aspect in the postproduction test since it is able to reduce the test data and the test costs, respectively. Current ATPG methods treat all faults independently from each other which limits the test compaction capabili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c36b0faa784fdb0440bc06e42d05e238
https://doi.org/10.1109/ets.2014.6847807
https://doi.org/10.1109/ets.2014.6847807
Publikováno v:
pp 93-100 (2014)
ATS
ATS
IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eda024265e67fa77198fb8ddd965bac0
https://lup.lub.lu.se/record/4731540
https://lup.lub.lu.se/record/4731540
Publikováno v:
DSD
This paper focuses on an industrial application of the proposed 1687 standard to significantly improve the test development effort and quality of test patterns for mixed signal IPs of an automotive design. The P1687 standard will enable the industry
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9ae8a0c8403507deb1ecf424a8ea3a9
https://doi.org/10.1109/dsd.2013.57
https://doi.org/10.1109/dsd.2013.57
Publikováno v:
DDECS
Numerous new multi-conditional fault models have been proposed in the last years. In combination with the increasing complexity of today's designs these new fault models cause a tremendous increases of the ATPG-runtime. In this paper we present a nov
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2cd34d5d8dd49020663b2dd7d3a848a9
https://doi.org/10.1109/ddecs.2013.6549786
https://doi.org/10.1109/ddecs.2013.6549786
Publikováno v:
DSD
This paper presents a highly robust approach to exactly analyze signal probabilities of Weighted Random Logic (WRL) BIST structures. WRL BIST structures are implemented in modern CMOS designs to ensure high defect coverage for example during on-line
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e09643794b43e77555adea78080eed5
https://doi.org/10.1109/dsd.2012.115
https://doi.org/10.1109/dsd.2012.115