Zobrazeno 1 - 10
of 35
pro vyhledávání: '"Renate Merker"'
Autor:
Renate Merker, Wolfgang Schwarz
Design automation of electronic and hybrid systems is a steadily growing field of interest and a permanent challenge for researchers in Electronics, Computer Engineering and Computer Science. System Design Automation presents some recent results in d
Publikováno v:
Journal of Circuits, Systems and Computers. 12:203-229
We present the design of a hardware–software system for the reconstruction of tomographic images. In a systematic approach we developed the parallel processor array, a reconfigurable hardware controller and processing kernel, and the software contr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9df2d8b84f2febb97b97abdc78da4e9d
https://doi.org/10.1142/s021812660300074x
https://doi.org/10.1142/s021812660300074x
Autor:
Renate Merker, Dirk Fimmel
Publikováno v:
The Journal of Supercomputing. 19:41-56
This paper deals with the design of processor arrays for regular algorithms. The design is constrained by limited implementation cost characterizing a reconfigurable architecture. The objective of the design is to minimize the latency of the processo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::570f1ba5349ba44316dbba831b4c24f6
https://doi.org/10.1023/a:1011136427062
https://doi.org/10.1023/a:1011136427062
Autor:
Dirk Fimmel, Renate Merker
Publikováno v:
Microprocessors and Microsystems. 22:149-155
This paper deals with the design of processor arrays for algorithms which can be represented as systems of uniform recurrence equations. We present an approach to determine allocation functions as part of this design. The objective of our approach is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73a5f1ead4883100158fc3aef2b75631
https://doi.org/10.1016/s0141-9331(98)00074-x
https://doi.org/10.1016/s0141-9331(98)00074-x
Publikováno v:
AEU - International Journal of Electronics and Communications. 69:151-152
On November 9, 2014 Professor Gerhard Wunsch will celebrate his 90th birthday. His impact as a scientist and teacher reaches far beyond the boundaries of the Dresden University of Technology (Technische Universitaet Dresden – TUD) to where he worke
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01d0c22edd2f40fe6aea8b4774c4a4f3
https://doi.org/10.1016/j.aeue.2014.08.008
https://doi.org/10.1016/j.aeue.2014.08.008
Autor:
Markus Rullmann, Renate Merker
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783642245671
ICSAMOS
ICSAMOS
We present a new model for dynamic reconfiguration costs. The model targets both, reconfiguration time and data. Reconfiguration is modeled at the granularity of reconfigurable resources, hence the model can take advantage of the partially identical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc3b2968c3a53b4bc679f2d700ae145c
https://doi.org/10.1007/978-3-642-24568-8_19
https://doi.org/10.1007/978-3-642-24568-8_19
Autor:
Markus Rullmann, Renate Merker
Publikováno v:
Dynamically Reconfigurable Systems ISBN: 9789048134847
Dynamically Reconfigurable Systems
Dynamically Reconfigurable Systems
In current FPGAs the overhead associated with partial dynamic reconfiguration limits the application of this method in system design. We review the origins of this overhead and present a novel approach to solve this problem. We introduce the reconfig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba3114b11b22674b0b3a022c94df2051
https://doi.org/10.1007/978-90-481-3485-4_8
https://doi.org/10.1007/978-90-481-3485-4_8
Publikováno v:
FPL
Efficient cycle-based reconfiguration of datapaths can be realized on current FPGAs by designing merged datapaths, which can execute different tasks depending on the datapath control. In our previous work, we provided a synthesis tool for the automat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abe86a3982a6e43f6b4f5a946288b08f
https://doi.org/10.1109/fpl.2009.5272540
https://doi.org/10.1109/fpl.2009.5272540
Publikováno v:
DSD
In this paper a systematic mapping method for a specific algorithm class is given which exploits all levels of parallelism of the target architecture. This target architecture is a processor array where each processing element can have several functi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::377ad8a94b77d53f31a4e1bb394d7463
https://doi.org/10.1109/dsd.2008.24
https://doi.org/10.1109/dsd.2008.24
Autor:
Renate Merker, Markus Rullmann
Publikováno v:
IPDPS
Dynamic reconfiguration for fine grained architectures is still associated with significant reconfiguration costs. In this paper we propose a new reconfiguration aware design flow. The tools in this flow implement a set of tasks concurrently. The flo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6422e89ff2f122658631165b2836279
https://doi.org/10.1109/ipdps.2007.370385
https://doi.org/10.1109/ipdps.2007.370385