Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Remy Berthelon"'
Autor:
Jie Liang, Chen Sun, Haiwen Xu, Eugene Y.-J. Kong, Bich-Yen Nguyen, Walter Schwarzenbach, Christophe Maleville, Remy Berthelon, Olivier Weber, Franck Arnaud, Aaron V.-Y. Thean, Xiao Gong
Publikováno v:
IEEE Transactions on Electron Devices. 69:1769-1775
Autor:
Simeon Morvan, E. Baylac, Emmanuel Josse, Michel Haond, Cyrille Le Royer, Olivier Gourhant, Didier Dutartre, Remy Berthelon, Francois Andrieu
Publikováno v:
ECS Transactions. 75:3-14
We have physically and electrically characterized pMOSFETs of compressively strained SiGe channel built on Ultra-Thin-Body and Buried-Oxide Fully-Depleted-Silicon-On-Insulator (UTBB FDSOI). Such a channel greatly contributes to the FDSOI CMOS high-pe
Autor:
John Morgan, Remy Berthelon, Jan Hoentschel, L. Pirro, G. Cibrario, Francois Andrieu, M. Wiatr, M. Vinet
Publikováno v:
2018 IEEE Symposium on VLSI Technology.
We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (V T -flavors) within a cell. It is successfully applied with nMOS Low-V T (LVT) and pMOS Super-Low-V T (SLVT) in Ultra-Low-Volt
Autor:
Franck Arnaud, Remy Berthelon, O. Rozeau, Olivier Weber, M. Vinet, Francois Andrieu, Bastien Giraud
Publikováno v:
2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).
In this work, we investigate the introduction of SiGe channel in FDSOI SRAM bitcells by the means of spice simulation. In classical SRAM configuration performance (read, write, retention) at a given leakage is only slightly impacted because of the Si
Autor:
Julien Claudon, Vincent Favre-Nicolin, Ondrej Mandula, Jean-Michel Gérard, Steven J. Leake, Marta Elzo-Aizarna, Joël Eymery, Francois Andrieu, Remy Berthelon, Gaétan Girard
Publikováno v:
Acta Crystallographica Section A Foundations and Advances
Acta Crystallographica Section A Foundations and Advances, International Union of Crystallography, 2017, 73 (a2), pp.C501-C501. ⟨10.1107/s2053273317090726⟩
Acta Crystallographica Section A : Foundations and Advances [2014-...]
Acta Crystallographica Section A : Foundations and Advances [2014-..], 2017, 73 (a2), pp.C501-C501. ⟨10.1107/s2053273317090726⟩
Acta Crystallographica Section A Foundations and Advances, International Union of Crystallography, 2017, 73 (a2), pp.C501-C501. ⟨10.1107/s2053273317090726⟩
Acta Crystallographica Section A : Foundations and Advances [2014-...]
Acta Crystallographica Section A : Foundations and Advances [2014-..], 2017, 73 (a2), pp.C501-C501. ⟨10.1107/s2053273317090726⟩
International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4a76fd7530c88f5825f1cc5e05a45941
https://hal.archives-ouvertes.fr/hal-01990220
https://hal.archives-ouvertes.fr/hal-01990220
Autor:
Gerard Ghibaudo, Claude Tabone, Emmanuel Josse, Joris Lacord, Franck Arnaud, Remy Berthelon, M. Vinet, Yann-Michel Niquet, C. Le Royer, L. Bourdet, Denis Rideau, Didier Dutartre, O. Rozeau, F. Andneu, Pascal Nguyen, Alain Claverie, M. Casse, S. Barraud, François Triozon
Publikováno v:
2017 VLSI-Technology Technical Digest
2017 IEEE Symposium on VLSI Technology
2017 IEEE Symposium on VLSI Technology, Jun 2017, Kyoto, Japan. pp.T224-T225, ⟨10.23919/VLSIT.2017.7998180⟩
2017 Symposium on VLSI Technology
2017 IEEE Symposium on VLSI Technology
2017 IEEE Symposium on VLSI Technology, Jun 2017, Kyoto, Japan. pp.T224-T225, ⟨10.23919/VLSIT.2017.7998180⟩
2017 Symposium on VLSI Technology
session 17: CMOS integration; International audience; We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e7a44e250cbeeaa54e79eb88b0ad7d87
https://hal.archives-ouvertes.fr/hal-02050220
https://hal.archives-ouvertes.fr/hal-02050220
Autor:
Alain Claverie, Remy Berthelon, Francois Andrieu, B. Mathieu, C. Le Royer, Didier Dutartre, M. Vinet
Publikováno v:
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
The ‘BOX creep’ technique consists in introducing stress in a SOI layer by taking advantage of the creep of the buried oxide enabled its low viscosity at high temperature. In this study, we deeply investigate the impact of the structure geometry
Autor:
C. Plantier, Pascal Besson, C. Le Royer, A. Bonnevialle, Michel Haond, Remy Berthelon, M. Vinet, Olivier Weber, M. Casse, S. Reboh, J-M. Pedini, Yves Morand, Alain Claverie, J.M. Hartmann, B. Mathieu, D. Rouchon, Francois Andrieu, Frederic Boeuf, D. Marseilhan, Sebastien Kerdiles, N. Rambal
Publikováno v:
VLSI Technology, 2016 IEEE Symposium on
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573406⟩
2016 IEEE Symposium on VLSI Technology
VLSI Technology, 2016 IEEE Symposium on, 2016, Unknown, Unknown Region. ⟨10.1109/VLSIT.2016.7573406⟩
2016 IEEE Symposium on VLSI Technology
cited By 1; International audience; We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. 'STRASS' and 'BOX creep' techniques (for tensily and compressively stressed channels, respectively) are for the fir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f40591e840f3628feb44812ad9fa4d18
https://hal.science/hal-01719489
https://hal.science/hal-01719489
Autor:
Denis Rideau, Vincent Delaye, Assawer Soussou, Marc Juhel, M. Casse, Francois Andrieu, Remy Berthelon, Gerard Ghibaudo, Gilles Reimbold, Charles Leroux, Clement Tavernier
Publikováno v:
ECS Transactions
ECS Transactions, Electrochemical Society, Inc., 2014, 64 (8), pp.61-68. ⟨10.1149/06408.0061ecst⟩
ECS Transactions, 2014, 64 (8), pp.61-68. ⟨10.1149/06408.0061ecst⟩
HAL
226th ECS and SMEQ Joint International Meeting: 12th Symposium on Semiconductors, Dielectrics and Metal for Nanoelectronics
226th ECS and SMEQ Joint International Meeting: 12th Symposium on Semiconductors, Dielectrics and Metal for Nanoelectronics, S. Kar, M. Houssa, H. Jagannathan, K. Kita, D. Landheer, D. Misra and S. Van Elshocht, Oct 2014, Cacun, Mexico
ECS Transactions, Electrochemical Society, Inc., 2014, 64 (8), pp.61-68. ⟨10.1149/06408.0061ecst⟩
ECS Transactions, 2014, 64 (8), pp.61-68. ⟨10.1149/06408.0061ecst⟩
HAL
226th ECS and SMEQ Joint International Meeting: 12th Symposium on Semiconductors, Dielectrics and Metal for Nanoelectronics
226th ECS and SMEQ Joint International Meeting: 12th Symposium on Semiconductors, Dielectrics and Metal for Nanoelectronics, S. Kar, M. Houssa, H. Jagannathan, K. Kita, D. Landheer, D. Misra and S. Van Elshocht, Oct 2014, Cacun, Mexico
International audience; By using the most advanced devices, simulations and electrical characterizations as well as physicochemical tools, this paper revisit the role of SiGe layers in the improvement of performances of pMOS transistors. It is shown
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::18b0d6df25c82ff923dcd0d7df787c88
https://hal.archives-ouvertes.fr/hal-01947593
https://hal.archives-ouvertes.fr/hal-01947593
Autor:
François Andrieu, Remy Berthelon, Simeon Morvan, Olivier Gourhant, Elise Baylac, Cyrille Le Royer, Didier Dutartre, Emmanuel Josse, Michel Haond
Publikováno v:
ECS Meeting Abstracts. :1954-1954
The 28 nm Ultra-Thin Body and Buried Oxide (UTBB) Fully Depleted Silicon-On-Insulator (FDSOI) technology is in production [4]. This technology addresses both high performance and low power / low voltage applications. Indeed, a 28 nm FDSOI Processor (