Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Remy Chevallier"'
Publikováno v:
2014 IEEE Radiation Effects Data Workshop (REDW).
We present Single Event Effects characterization and Total Ionizing Dose behavior up to 300 krad(Si) on Rad-Hardened 1.2GHz PLL IP and cold-spare I/O from new ST CMOS 65nm space technology.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a71a7cab419cd634a5a175d3628d6345
https://doi.org/10.1109/redw.2014.7004601
https://doi.org/10.1109/redw.2014.7004601
Autor:
E. Pion, P. Larre, D. Ney, Remy Chevallier, Vincent Huard, Thierry Parrassin, Damien Croain, Alain Bravaix, Anand Kumar Mishra, Xavier Federspiel
Publikováno v:
2013 IEEE International Reliability Physics Symposium (IRPS).
This paper introduces for the first time a new test structure for electromigration which allows increased statistics and reliability tests in a testchip under typical High Temperature Operating Life experimental ranges. Following the electrical analy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83af8a30aeb207174ae2a5ea1cd9a295
https://doi.org/10.1109/irps.2013.6532001
https://doi.org/10.1109/irps.2013.6532001
Publikováno v:
2011 International Reliability Physics Symposium.
As CMOS technology continues to downscale to a deep submicron level (40 nm and beyond), Soft Oxide Breakdown (SBD) is becoming a real problem that could lead to a serious degradation in the performances and the functional operations of SoC. In this p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e120bf8d9b132d83902d8c7553aa4f1
https://doi.org/10.1109/irps.2011.5784561
https://doi.org/10.1109/irps.2011.5784561
Publikováno v:
Formal Methods in System Design
Formal Methods in System Design, Springer Verlag, 2009, 34 (1), pp.59-81. ⟨10.1007/s10703-008-0061-x⟩
Formal Methods in System Design, 2009, 34 (1), pp.59-81. ⟨10.1007/s10703-008-0061-x⟩
Formal Methods in System Design, Springer Verlag, 2009, 34 (1), pp.59-81. ⟨10.1007/s10703-008-0061-x⟩
Formal Methods in System Design, 2009, 34 (1), pp.59-81. ⟨10.1007/s10703-008-0061-x⟩
International audience; Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we analyse some crucial timing behaviors of the architecture of SPSMALL memory, a commercial product of STMicroelectronics. Using
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::62a70cb4f78413f53abddeb8fc1476ad
https://hal.archives-ouvertes.fr/hal-01195912
https://hal.archives-ouvertes.fr/hal-01195912
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540450269
FORMATS
FORMATS
Using a variant of Clariso-Cortadella’s parametric method for verifying asynchronous circuits, we formally derive a set of linear constraints that ensure the correctness of some crucial timing behaviours of the architecture of SPSMALL memory. This
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0d5ad7278c35d765befe2a0b19c42106
https://doi.org/10.1007/11867340_9
https://doi.org/10.1007/11867340_9
Publikováno v:
ACM Great Lakes Symposium on VLSI
We present a property verification method for behavioral descriptions with TheoSim, a tool that combines symbolic simulation and automatic reasoning. The effectiveness of the method is illustrated on the verification of SPSMALL, a memory designed by
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c97149ab1dd0b4c7578989b8b2c1802
https://doi.org/10.1145/1057661.1057724
https://doi.org/10.1145/1057661.1057724
Publikováno v:
2014 IEEE Radiation Effects Data Workshop (REDW); 2014, p1-8, 8p
Autor:
Etienne André, Romain Soulat
This book introduces state-of-the-art verification techniques for real-time embedded systems, based on the inverse method for parametric timed automata. It reviews popular formalisms for the specification and verification of timed concurrent systems
Autor:
Eugene Asarin, Patricia Bouyer
This volume contains the proceedings of the 4th International Conference on Formal Modelling and Analysis of Timed Systems (FORMATS 2006), held in Paris (France) on September 25-27, 2006. FORMATS aims to be a major - nual event dedicated to the study