Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Remo Kirsch"'
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 29:299-305
Design Hotspots are features on a silicon chip, which are susceptible to pattern failures. While multiple methods like DRC, ORC, and in-line defect inspection are used to identify these hotspots, in-line monitoring of these Design Hotspots has remain
Publikováno v:
2015 26th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Design Hotspots are features on a silicon chip, which are susceptible to pattern failures. While multiple methods like DRC, ORC and CFM inspection are used to identify these Hotspots, in-line monitoring of these design Hotspots has remained a challen
Autor:
Mirko Beyer, Tobias Gunther, Dan Koronel, Vijeet Gupta, Govinda Soni, Torsten Billasch, Christophe Soonekindt, Robert van Oostrum, Remo Kirsch
Publikováno v:
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
In this paper we demonstrate a sensitivity improvement on a Nitride Strip layer at the Shallow Trench Isolation (STI) process module and how this sensitivity was later used to improve yield monitoring. The improvement was enabled due to optics enhanc
Publikováno v:
SPIE Proceedings.
As semiconductor process design rules continue to shrink, the ability of optical inspection tools to separate between true defects and nuisance becomes more and more difficult. Therefore, monitoring Defect of Interest (DOI) become a real challenge (F
Publikováno v:
SPIE Proceedings.
Reticle defectivity has been a widely discussed topic in the last few years primarily due to ongoing haze issues but also because of the increasing number of the qualification methods available in the fab. Mask shops are taking a closer look at the a
Autor:
Uzodinma Okoroanyanwu, Remo Kirsch, Antje Martin, Wolfram Grundke, Eran Valfer, Susan Weiher-Tellford, Ute Vogler, Nurit Racah, Richard Moerman, Mirko Beyer, Renana Perlovitch, Peter Vanoppen
Publikováno v:
SPIE Proceedings.
Immersion lithography addresses the limits of optical lithography by providing higher NA's (NA > 1), which enable imaging of smaller features and hence it enables production of 45nm logic devices. One of the key challenges of this advanced technology
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