Zobrazeno 1 - 10
of 130
pro vyhledávání: '"Reineke, Jan"'
Publikováno v:
IEEE International Symposium on Workload Characterization, IISWC 2023, Ghent, Belgium, October 1-3, 2023
Basic-block throughput models such as uiCA, IACA, GRANITE, Ithemal, llvm-mca, OSACA, or CQA guide optimizing compilers and help performance engineers identify and eliminate bottlenecks. For this purpose, basic-block throughput models should ideally b
Externí odkaz:
http://arxiv.org/abs/2310.13212
Autor:
Touzeau, Valentin, Reineke, Jan
While instruction cache analysis is essentially a solved problem, data cache analysis is more challenging. In contrast to instruction fetches, the data accesses generated by a memory instruction may vary with the program's inputs and across dynamic o
Externí odkaz:
http://arxiv.org/abs/2310.04809
Autor:
Reineke, Jan
Publikováno v:
Leibniz Transactions on Embedded Systems, Vol 5, Iss 1, Pp 03:1-03:52 (2018)
We clarify the notion of cache persistence and contribute to the understanding of persistence analysis for caches with least-recently-used replacement.To this end, we provide the first formal definition of persistence as a property of a trace semanti
Externí odkaz:
https://doaj.org/article/59717ac8221845f7a6ae2d3cd1263b3e
Leakage contracts have recently been proposed as a new security abstraction at the Instruction Set Architecture (ISA) level. Such contracts aim to faithfully capture the information processors may leak through side effects of their microarchitectural
Externí odkaz:
http://arxiv.org/abs/2305.06979
Publikováno v:
Leibniz Transactions on Embedded Systems, Vol 3, Iss 1, Pp 05:1-05:48 (2016)
Real-time systems are reactive computer systems that must produce their reaction to a stimulus within given time bounds. A vital verification requirement is to estimate the Worst-Case Execution Time (WCET) of programs. These estimates are then used t
Externí odkaz:
https://doaj.org/article/2857c05012294b51a8fa177b507bace4
Autor:
Reineke, Jan
Publikováno v:
Leibniz Transactions on Embedded Systems, Vol 1, Iss 1, Pp 03:1-03:13 (2014)
We investigate the suitability of caches with randomized placement and replacement in the context of hard real-time systems. Such caches have been claimed to drastically reduce the amount of information required by static worst-case execution time (W
Externí odkaz:
https://doaj.org/article/49fb22af0d5e4838b5b302c21e1663a6
Autor:
Morelli, Canberk, Reineke, Jan
Techniques to evaluate a program's cache performance fall into two camps: 1. Traditional trace-based cache simulators precisely account for sophisticated real-world cache models and support arbitrary workloads, but their runtime is proportional to th
Externí odkaz:
http://arxiv.org/abs/2203.14845
Autor:
Abel, Andreas, Reineke, Jan
Publikováno v:
2022 International Conference on Supercomputing (ICS '22), June 28--30, 2022, Virtual Event, USA
Performance models that statically predict the steady-state throughput of basic blocks on particular microarchitectures, such as IACA, Ithemal, llvm-mca, OSACA, or CQA, can guide optimizing compilers and aid manual software optimization. However, the
Externí odkaz:
http://arxiv.org/abs/2107.14210
Since the discovery of Spectre, a large number of hardware mechanisms for secure speculation has been proposed. Intuitively, more defensive mechanisms are less efficient but can securely execute a larger class of programs, while more permissive mecha
Externí odkaz:
http://arxiv.org/abs/2006.03841
Flushing the cache, using instructions like clflush and wbinvd, is commonly proposed as a countermeasure against access-based cache attacks. In this report, we show that several Intel caches, specifically the L1 caches in some pre-Skylake processors
Externí odkaz:
http://arxiv.org/abs/2005.13853