EEPROM endurance degradation at different temperatures: State of the art TCAD simulation

Autor: Matteo, Franck, Coulié, Karine, Simola, Roberto, Postel-Pellerin, Jérémy, Melul, Franck, Regnier, Arnaud

Publikováno v: In Microelectronics Reliability September 2022 136

Experimental setup for non-destructive measurement of tunneling currents in semiconductor devices

Autor: Chiquet, Philippe, Masson, Pascal, Postel-Pellerin, Jérémy, Laffont, Romain, Micolau, Gilles, Lalande, Frédéric, Regnier, Arnaud

Publikováno v: In Measurement August 2014 54:234-240

Modeling Halo Implant Failures in MOS Sub-Micron Technology

Autor: Regnier, Arnaud, Portal, Jean-Michel, Bouchakour, Rachid, Renovell, Michel

Publikováno v: 6th IEEE Latin American Test Workshop
LATW: Latin American Test Workshop
LATW: Latin American Test Workshop, Mar 2005, Salvador, Bahia, Brazil. pp.29-33

International audience

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::45f4a220f7de242555dc14fcb037995d
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00106513

Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.

Autor: Innocenti, Jordan, Welter, Loic, Julien, Franck, Lopez, Laurent, Sonzogni, Jacques, Niel, Stephan, Regnier, Arnaud, Paire, Emmanuel, Labory, Karen, Denis, Eric, Portal, Jean-Michel, Masson, Pascal

Publikováno v: 2014 IEEE 57th International Midwest Symposium on Circuits & Systems (MWSCAS); 2014, p897-900, 4p

Non volatile memory reliability prediction based on oxide defect generation rate during stress and retention tests.

Autor: Aziza, Hassen, Portal, J-Michel, Plantier, Jeremy, Reliaud, Christine, Regnier, Arnaud, Ogier, J-Luc

Publikováno v: 2011 International Semiconductor Device Research Symposium (ISDRS); 2011, p1-2, 2p