Zobrazeno 1 - 10
of 2 346
pro vyhledávání: '"Registered memory"'
Autor:
Nagi Mekhiel
Publikováno v:
IEEE Access, Vol 4, Pp 1073-1085 (2016)
The increase in processor speed achieved by continuous improvements in technology is causing major obstacles to the parallel processors implemented inside the chip. The time spent in servicing all the cache misses from all processors from a slow shar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9707809215befd5c7926517fcf57f4d1
https://doi.org/10.32920/21463020
https://doi.org/10.32920/21463020
Autor:
David Harris, Sarah L. Harris
Publisher Summary This chapter explores memory system organization. It is a major factor in determining computer performance. Different memory technologies such as dynamic random-access memory (DRAM), static random-access memory (SRAM), and hard disk
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::957a62b94d754e04ee23a8fc804f478d
https://doi.org/10.1016/b978-0-12-820064-3.00008-8
https://doi.org/10.1016/b978-0-12-820064-3.00008-8
Autor:
Wooyoung Jang
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 28:3527-3538
The state-of-the-art mobile image and graphic applications demand not only a lot of computing power, but also high-quality memory services. Moreover, depending on the screen orientations of mobile systems, image and graphic data can be accessed in a
Publikováno v:
IPDPS Workshops
Remote Direct Memory Access (RDMA) is an increasingly important technology in high-performance computing (HPC). RDMA provides low-latency, high-bandwidth data transfer between compute nodes. Additionally, it does not require explicit synchronization
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:307-318
The gradually widening disparity in the speed of the CPU and memory has become a bottleneck for the development of chip multiprocessor (CMP) systems. Increasing penalties caused by frequent on-chip memory access have raised critical challenges in del
Publikováno v:
IEEE Computer Architecture Letters. 17:5-8
Many studies focus on implementing processing-in memory (PIM) on the logic die of the hybrid memory cube (HMC) architecture. The multiply-accumulate (MAC) operation is heavily used in digital signal processing (DSP) systems. In this paper, a novel PI
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:3484-3494
In this paper, we present embedded dynamic random access memory (eDRAM)-based memory customization techniques for low-cost fast Fourier transform (FFT) processor design. The main idea is based on the observation that the FFT processor has regular and
Publikováno v:
IEEE Transactions on Parallel and Distributed Systems. 28:3188-3200
Multi-Level Cell Phase Change Memory (MLC PCM) is a promising candidate technology for DRAM replacement in main memory of modern computers. Despite of its high density and low power advantages, this technology seriously suffers from slow read and wri
Publikováno v:
IEEE Transactions on Magnetics. 53:1-4
In the current big data era, the memory wall issue between the processor and the memory becomes one of the most critical bottlenecks for conventional Von-Newman computer architecture. In-memory processing (IMP) or near-memory processing (NMP) paradig
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36:1674-1687
Parallelizing the memory accesses in a nested loop is a critical challenge to facilitate loop pipelining. An effective approach for high-level synthesis on field-programmable gate array is to map these accesses to multiple on-chip memory banks using