SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems

Autor: Razi Seyyedi, Roman Obermaisser, Javier Coronel, Alfons Crespo, J.C. García, Mohamed Tagelsir Mohammadat, Johnny Öberg, Sören Schreiner, Alina Lenz, Adele Maleki, Nera González Romero, Jon Perez, Mikel Azkarate-askasua, Ingo Sander, Kim Grüttner, Ingemar Söderquist, Simon Davidmann, Maher Fakih

Publikováno v: Microprocessors and Microsystems. 52:89-105

With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::392bd11d4258a076ef39b08a4b5302ac
https://doi.org/10.1016/j.micpro.2017.05.016

Functional test environment for time-triggered control systems in complex MPSoCs

Autor: Kim Grüttner, Maher Fakih, Wolfgang Nebel, Sören Schreiner, Razi Seyyedi

Publikováno v: Microprocessors and Microsystems. 76:103072

Many safety-critical and especially mixed-criticality computer systems are realized as a time-triggered (TT) system. Such systems execute one or more tasks according to a pre-determined scheduling. For the integration of functionality on such a TT MP

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::12f13eb23172e44ec2aa26c1fbb7a7c5
https://doi.org/10.1016/j.micpro.2020.103072

Towards power management verification of time-triggered systems using virtual platforms

Autor: Razi Seyyedi, Maher Fakih, Kim Grüttner, Sören Schreiner, Wolfgang Nebel

Publikováno v: SAMOS

Mixed-Criticality Real-Time Embedded Systems (MCRTES) allow the integration of independent functions with different safety requirements. Furthermore, the implementation of MCRTES on Multiprocessor system-on-chips (MPSoC) is becoming more and more int

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6b1724fae6b001918f47366b9a2a7875
https://doi.org/10.1145/3229631.3235025

Experimental Evaluation of SAFEPOWER Architecture for Safe and Power-Efficient Mixed-Criticality Systems

Autor: Tage Mohammadat, Salvador Peiro Frasquet, Patricia Balbastre, Yosab Bebawy, Timmy Sundström, Roman Obermaisser, Johnny Öberg, Elena Quesada Gonzalez, Adele Maleki, Duncan Graham, Mikel Azkarate-askasua, Sören Schreiner, Alina Lenz, Nera González Romero, Kim Grüttner, Razi Seyyedi, Peio Onaindia, Maher Fakih, Tomaso Poggi

Publikováno v: Journal of Low Power Electronics and Applications
Volume 9
Issue 1
Journal of Low Power Electronics and Applications, Vol 9, Iss 1, p 12 (2019)

With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ccaf10d895ddea0b54ed497e6f2810f5
https://doi.org/10.3390/jlpea9010012

Protecting SRAM-based FPGAs Against Multiple Bit Upsets Using Erasure Codes

Autor: Mehdi B. Tahoori, Razi Seyyedi, Mojtaba Ebrahimi, Parthasarathy M. B. Rao

Publikováno v: DAC

Multiple bit upsets due to radiation-induced soft errors are a major concern in nanoscale technology nodes. Once such errors occur in the configuration frames of an FPGA device, they permanently affect the functionality of the mapped design. The comb

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::48035653d3c2f26fc71c5a4662e99a9e
https://doi.org/10.1145/2593069.2593191