Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Raymond R Hoare"'
Publikováno v:
2022 IEEE International Symposium on Phased Array Systems & Technology (PAST).
Autor:
Raymond R. Hoare, Swapna Dontharaju, Marlin H. Mickle, Shenchih Tung, Alex K. Jones, James T. Cain
Publikováno v:
RFID Handbook ISBN: 9781315219325
RFID Handbook
RFID Handbook
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1c63160df6d096b045cdde9f62f8d0c2
https://doi.org/10.1201/9781420055009-3
https://doi.org/10.1201/9781420055009-3
Publikováno v:
Journal of Parallel and Distributed Computing. 68:1437-1451
Greedy scheduling heuristics provide a low complexity and scalable albeit particularly sub-optimal strategy for hardware-based crossbar schedulers. In contrast, the maximum matching algorithm for Bipartite graphs can be used to provide optimal schedu
Autor:
Marlin H. Mickle, Alex K. Jones, Raymond R. Hoare, James T. Cain, Shenchih Tung, Leo Mats, Peter J. Hawrylak, Swapna Dontharaju
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 13:1-22
While RFID is starting to become a ubiquitious technology, the variation between different RFID systems still remains high. This paper presents several prototyping environments for different components of radio frequency identification (RFID) tags to
Autor:
Alex K. Jones, Ralph Sprang, James T. Cain, Raymond R. Hoare, Joshua Fazekas, Marlin H. Mickle, Swapna Dontharaju, Shenchih Tung
Publikováno v:
Microprocessors and Microsystems. 31:116-134
The use of radio frequency identification (RFID) technology is expanding rapidly in numerous applications such as logistics, supply chain management, transportation, healthcare and aviation. Due to the variety of the current applications, typical RFI
Publikováno v:
Microprocessors and Microsystems. 30:445-456
The growing complexity of Field Programmable Gate Arrays (FPGA’s) is leading to architectures with high input cardinality look-up tables (LUT’s). This paper describes a methodology for area-optimal combinational technology mapping, specifically d
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 53:1250-1254
This brief presents a heterogeneous multicore embedded processor architecture designed to exceed performance of traditional embedded processors while reducing the power consumed compared to low-power embedded processors. At the heart of this architec
Publikováno v:
ACM Transactions on Embedded Computing Systems. 5:658-686
Multiprocessor Systems on Chips (MPSoCs) have become a popular architectural technique to increase performance. However, MPSoCs may lead to undesirable power consumption characteristics for computing systems that have strict power budgets, such as PD
Autor:
Brady Hunsaker, Justin Stander, Gayatri Mehta, Alex K. Jones, Raymond R. Hoare, Joshua M. Lucas
Publikováno v:
Journal of Low Power Electronics. 2:148-164
Publikováno v:
EURASIP Journal on Embedded Systems, Vol 2006, Iss 1, p 048085 (2006)
EURASIP Journal on Embedded Systems, Vol 2006 (2006)
EURASIP Journal on Embedded Systems, Vol 2006 (2006)
This paper examines the design of an FPGA-based system-on-a-chip capable of performing continuous speech recognition on medium sized vocabularies in real time. Through the creation of three dedicated pipelines, one for each of the major operations in