Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Raymond M. Sicina"'
Autor:
Kathryn W. Guarini, Guy M. Cohen, H.J. Hovel, J. Benedict, C. Cabral, K. Petrarca, Diane C. Boyd, Raymond M. Sicina, J.H. Yoon, J. Newbury, P. Kozlowski, Paul M. Solomon, Hon-Sum Philip Wong, Christopher P. D'Emic, A. Krasnoperova, M. Ronay, K.K. Chan, V. Ku, O. Dokumaci, Christian Lavoie, Inna V. Babich, J.J. Bucchignano, E.C. Jones, J. Treichler, Y. Zhang
Publikováno v:
IEEE Circuits and Devices Magazine. 19:48-62
A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76dcf51997d0234eec7ae42db2413164
https://doi.org/10.1109/mcd.2003.1175108
https://doi.org/10.1109/mcd.2003.1175108
Autor:
Christopher P. D'Emic, Paul C. Jamison, Min Yang, A.I. Chou, P. Kozlowski, Diane C. Boyd, Oleg Gluschenkov, Raymond M. Sicina, Evgeni Gusev, K.K. Chan, Meikei Ieong
Publikováno v:
IEEE Electron Device Letters. 24:339-341
Dependence of CMOS performance on silicon crystal orientation of [100], [111], and [110] has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of /spl ges/160% has been observed for both oxynitr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1f69d8f95d808a229bd3db0c3cfa114
https://doi.org/10.1109/led.2003.812565
https://doi.org/10.1109/led.2003.812565
Autor:
C. Cabral, Diane C. Boyd, E.C. Jones, Kathryn W. Guarini, K.K. Chan, J. Treichler, J.J. Bucchignano, Victor Ku, J. Newbury, Y. Zhang, Hon-Sum Philip Wong, A. Krasnoperova, Christopher P. D'Emic, Raymond M. Sicina, M. Ronay, O. Dokumaci, Guy M. Cohen, P. Kozlowski, Christian Lavoie, Paul M. Solomon, Inna V. Babich, K.S. Petrarca
Publikováno v:
International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
We introduce a planar, triple-self-aligned double-gate FET structure ("PAGODA"). Device fabrication incorporates wafer bonding, front-end CMP, mixed optical/e-beam lithography, silicided silicon source/drain sidewalls, and back gate undercut and pass
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4572bd937899028c07a85604ae8a1c8
https://doi.org/10.1109/iedm.2001.979527
https://doi.org/10.1109/iedm.2001.979527