Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Ravindra Jejurikar"'
Autor:
Chandranan Dhar, Jordan Ethan, Ravindra Jejurikar, Mustafa Khairallah, Eik List, Sougata Mandal
Publikováno v:
IACR Transactions on Symmetric Cryptology, Vol 2024, Iss 2 (2024)
During recent years, research on authenticated encryption has been thriving through two highly active and practically motivated research directions: provable leakage resilience and key- or context-commitment security. However, the intersection of bot
Externí odkaz:
https://doaj.org/article/8e1541836cb34ba290ba0b2e4a2cd773
Autor:
Rajesh Gupta, Ravindra Jejurikar
Publikováno v:
IEEE Transactions on Computers. 55:1588-1598
Slowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic voltage scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings. We a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e6bcc54710e5d7ccdfa94848e9cfc41e
https://doi.org/10.1109/tc.2006.204
https://doi.org/10.1109/tc.2006.204
Autor:
Ravindra Jejurikar, Rajesh Gupta
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:1024-1037
Slowdown factors determine the extent of slowdown that a computing system can experience based on functional and performance requirements. Dynamic voltage scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c494435febd3f6ca2f48a0a260ec376
https://doi.org/10.1109/tcad.2005.855964
https://doi.org/10.1109/tcad.2005.855964
Autor:
Rajesh Gupta, Ravindra Jejurikar
Publikováno v:
DAC
Leakage energy consumption is an increasing concern in current and future CMOS technology generations. Procrastination scheduling, where task execution can be delayed to maximize the duration of idle intervals, has been proposed to minimize leakage e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ca841fac4b9562f0daa886a1c6fe4fd
https://doi.org/10.1145/1065579.1065612
https://doi.org/10.1145/1065579.1065612
Autor:
Ravindra Jejurikar, Rajesh Gupta
Publikováno v:
ISLPED
Traditionally, dynamic voltage scaling (DVS) techniques have focused on minimizing the processor energy consumption as opposed to the entire system energy consumption. The slowdown resulting from DVS can increase the energy consumption of components
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a84f7210590223ac8d2ea0f7751afe4c
https://doi.org/10.1145/1013235.1013261
https://doi.org/10.1145/1013235.1013261
Autor:
Rajesh Gupta, Ravindra Jejurikar
Publikováno v:
LCTES
Procrastination scheduling has gained importance for energy efficiency due to the rapid increase in the leakage power consumption. Under procrastination scheduling, task executions are delayed to extend processor shutdown intervals, thereby reducing
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6233233c133a5f3f0cfc866d97cd098f
https://doi.org/10.1145/997163.997173
https://doi.org/10.1145/997163.997173
Publikováno v:
DAC
A five-fold increase in leakage current is predicted with each technology generation. While Dynamic Voltage Scaling (DVS) is known to reduce dynamic power consumption, it also causes increased leakage energy drain by lengthening the interval over whi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aca513940549da9d9f7c5e6e88c68d61
https://doi.org/10.1145/996566.996650
https://doi.org/10.1145/996566.996650
Autor:
Rajesh Gupta, Ravindra Jejurikar
Publikováno v:
CASES
Slowdown factors determine the extent of slowdown a computing system can experience based on functional and performance requirements. Dynamic Voltage Scaling (DVS) of a processor based on slowdown factors can lead to considerable energy savings. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a6e29badf8adad31c05f5f0a8c018c9b
https://doi.org/10.1145/581630.581655
https://doi.org/10.1145/581630.581655
Publikováno v:
ASP-DAC
Advances in microelectronics integration have led to the emergence of tightly integrated systems with high performance network interfaces. Design of such systems especially for single chip implementation is a delicate balance of functionality and ava
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cec393a2ac553fb5ae4548d679764c51
https://doi.org/10.1145/368434.368589
https://doi.org/10.1145/368434.368589