Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Ratna Krishnamoorthy"'
Autor:
Masahiro Fujita, Ratna Krishnamoorthy, S. K. Nandy, Keshavan Varadarajan, Saptarsi Das, Mythri Alle, Ranjani Narayan
Publikováno v:
IPSJ Transactions on System LSI Design Methodology. 4:193-209
Coarse Grain Reconfigurable Architectures (CGRA) support spatial and temporal computation to speedup execution and reduce reconfiguration time. Thus compilation involves partitioning instructions spatially and scheduling them temporally. The task of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0cafbb232481034aebd1f5df8ffe79b
https://doi.org/10.2197/ipsjtsldm.4.193
https://doi.org/10.2197/ipsjtsldm.4.193
Autor:
Wai Teng Tang, Rick Siow Mong Goh, Wen Jun Tan, Weng-Fai Wong, Yi Wen Wong, Stephen John Turner, Ratna Krishnamoorthy, Shyh-hao Kuo
Publikováno v:
IPDPS
Stencils represent an important class of computations that are used in many scientific disciplines. Increasingly, many of the stencil computations in scientific applications are being offloaded to GPUs to improve running times. Since a large part of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc407c950a219ae3b1d99643edc6521f
https://doi.org/10.1109/ipdps.2013.79
https://doi.org/10.1109/ipdps.2013.79
Interconnect-topology independent mapping algorithm for a Coarse Grained Reconfigurable Architecture
Publikováno v:
FPT
Mapping applications onto a Coarse Grained Re-configurable Architecture (CGRA) requires knowledge about the interconnect topology used on the reconfigurable fabric. In order to make communication as efficient as possible, the application sub-structur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b523671d836b261a1f92fcbe582214c0
https://doi.org/10.1109/fpt.2011.6132677
https://doi.org/10.1109/fpt.2011.6132677
Autor:
Masahiro Fujita, S. K. Nandy, Keshavan Varadarajan, Ranjani Narayan, Ratna Krishnamoorthy, Mythri Alle
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783642194740
ARC
ARC
Coarse Grain Reconfigurable Architectures(CGRA) support Spatial and Temporal computation to speedup execution and reduce reconfiguration time. Thus compilation involves partitioning instructions spatially and scheduling them temporally. We extend Edg
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82337ae4b28ec8b23f17cfabee24c7ee
https://doi.org/10.1007/978-3-642-19475-7_15
https://doi.org/10.1007/978-3-642-19475-7_15
Autor:
Masahiro Fujita, Ratna Krishnamoorthy, Mythri Alle, Keshavan Varadarajan, S. K. Nandy, Ranjani Narayan, Ganesh Garga
Publikováno v:
CASES
In Dynamically Reconfigurable Processors (DRPs), compilation involves breaking an application into sub-tasks for piecewise execution on the fabric. These sub-tasks are sequenced based on data and control dependences. In DRPs, sub-task prefetching is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75b592dd7d16811bb7d8dbe162036744
https://doi.org/10.1145/1878921.1878935
https://doi.org/10.1145/1878921.1878935