Zobrazeno 1 - 10
of 45
pro vyhledávání: '"Randy W. Mann"'
Autor:
Xi Cao, Jack M. Higman, Rick Carter, O Sung Kwon, Joseph Versaggi, M. A. Karim, Randy W. Mann, Sanjay Parihar, Meixiong Zhao
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:1341-1344
In this brief, we investigate device variability in advanced fin field effect transistor (FinFET) static random access memory (SRAM) devices (12 and 7 nm) as a function of drain-to-source (Vds) bias. Drain-induced barrier lowering (DIBL) and the vari
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11d778152eec53c7d4a7cfccc1417f28
https://doi.org/10.1109/tvlsi.2020.2974202
https://doi.org/10.1109/tvlsi.2020.2974202
Autor:
Rick Carter, Joseph Versaggi, Jack M. Higman, Randy W. Mann, Shesh Mani Pandey, Meixiong Zhao, Sanjay Parihar, Carl J. Radens, Qun Gao, Ankur Arya
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27:1819-1827
A previously unrecognized vertical-extrinsic device in advanced 7-nm FinFET SRAM structures is identified and characterized for the first time. The ON-current for this vertical-extrinsic device is modulated by gate bias and exhibits a process-depende
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::77d7ed39ce0662d0814bdbcfd9a24f0a
https://doi.org/10.1109/tvlsi.2019.2907594
https://doi.org/10.1109/tvlsi.2019.2907594
Autor:
Michael Gribelyuk, Sandeep Puri, C. Weintraub, Xiaoqiang Zhang, Sheng Xie, Joseph Versaggi, Randy W. Mann, Bianzhu Fu, Hui Zang, Daniel Marienfeld, Ratheesh R. Thankalekshmi
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:2449-2457
An essential goal of the static random access memory (SRAM) array termination design is to both terminate as well as maintain a homogeneous environment for the active edge cells in the array. Local layout effects (LLEs) in the array termination desig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb2142d8c923da7e8f29f60ba4cedd2f
https://doi.org/10.1109/tvlsi.2017.2713124
https://doi.org/10.1109/tvlsi.2017.2713124
Autor:
Yoann Mamy Randriamihaja, C. Weintraub, Sheng Xie, Akhilesh Gautam, Yuncheng Song, B. Parameshwaran, William McMahon, Randy W. Mann, Joseph Versaggi, Ajay Anand Kallianpur
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:660-669
A novel bias-induced healing of address specific failing bits in VLSI SRAM functional arrays is demonstrated for the first time in advanced CMOS nodes. Aging effects due to bias temperature instability (BTI) resulting in device shifts are a well-know
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::220978529010688277eaafbb52eb2f09
https://doi.org/10.1109/tvlsi.2016.2598160
https://doi.org/10.1109/tvlsi.2016.2598160
Autor:
Daniel Marienfeld, Randy W. Mann, Lucile C. Teague Sheridan, Yuncheng Song, Chong Khiam Oh, Joseph Versaggi, Sheng Xie, Dirk Fimmel, Wolfgang Finger, Dapeng Sun, Matthias Hoffmann
Publikováno v:
2019 IEEE 11th International Memory Workshop (IMW).
This work reports the application of an ultra-fast insitu characterization capability in SRAM array in advanced nodes. The methodology was tested in fully functional SRAM arrays in 14 nm and 7 nm FinFET nodes, allowing assessment of individual device
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e07528e71def4ad442e734cdc156d1b9
https://doi.org/10.1109/imw.2019.8739413
https://doi.org/10.1109/imw.2019.8739413
Publikováno v:
IOLTS
Aggressive technology and supply voltage scaling has led to increasing concern for reliability. Optimizing power and energy with sub-threshold (sub-V T ) operation exponentially increases the occurrences of both static and dynamic failures. With smal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::685a7e8baf18632f322b0877802148fb
https://doi.org/10.1109/iolts.2017.8046222
https://doi.org/10.1109/iolts.2017.8046222
Autor:
Stuart N. Wooters, Randy W. Mann, Mircea R. Stan, Travis N. Blalock, Zhenyu Qi, Adam C. Cabe, Jiajing Wang, Benton H. Calhoun
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1974-1985
Recent works show bias temperature instability (BTI) is a detrimental hard-aging mechanism in CMOS circuit design. Negative BTI (NBTI) alone degrades circuit speed upwards of 20% over a 10 year life-span. Having the ability to track the actual aging
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3f43303ff8d4afe2101573314ca6611
https://doi.org/10.1109/tvlsi.2011.2168246
https://doi.org/10.1109/tvlsi.2011.2168246
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1211-1220
Competitive density, performance, and functional objectives of the SRAM bit cell require design rules which are much more aggressive than those used in base logic designs. Because soft fail yield in SRAM is dependent on the device threshold and thres
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::948acfc8b23642c60bca86705528ca41
https://doi.org/10.1109/tvlsi.2011.2158863
https://doi.org/10.1109/tvlsi.2011.2158863
Autor:
Geordie Braceras, Satyanand Nalam, Jiajing Wang, Sudhanshu Khanna, Randy W. Mann, Harold Pilo, Benton H. Calhoun
Publikováno v:
Solid-State Electronics. 54:1398-1407
Large scale 6T SRAM beyond 65 nm will increasingly rely on assist methods to overcome the functional limitations associated with scaling and the inherent read stability/write margin trade off. The primary focus of the circuit assist methods has been
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::23e19e9e7dd142a1a81c37878effd682
https://doi.org/10.1016/j.sse.2010.06.009
https://doi.org/10.1016/j.sse.2010.06.009
Autor:
Torsten Klick, Vivek Joshi, Fan Chen, Akash Kumar, Rakesh Ranjan, Yuncheng Song, T. Schaefer, Randy W. Mann, William McMahon, Sriram Balasubramanian, T. Nigam, Y. Mamy Randriamihaja, B. Parameshwaran
Publikováno v:
IRPS
Extended 6 Transistors (6T) SRAM (Static Random-Access Memory) characterization is used to measure degradation while separating intrinsic from extrinsic yield and accounting for yield assessment challenges such as voltage drop and measurement variabi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::607166eea23089f10338cdd99e41ed29
https://doi.org/10.1109/irps.2015.7112759
https://doi.org/10.1109/irps.2015.7112759