Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Ranasinghe, Waruna"'
This paper studies two variants of tiling: iteration space tiling (or loop blocking) and cache-oblivious methods that recursively split the iteration space with divide-and-conquer. The key question to answer is when we should be using one over the ot
Externí odkaz:
http://arxiv.org/abs/1802.00166
Autor:
Jin, Tian, Prajapati, Nirmal, Ranasinghe, Waruna, Iooss, Guillaume, Zou, Yun, Rajopadhye, Sanjay, Wonnacott, David
Polyhedral compilers perform optimizations such as tiling and parallelization; when doing both, they usually generate code that executes "barrier-synchronized wavefronts" of tiles. We present a system to express and generate code for hybrid schedules
Externí odkaz:
http://arxiv.org/abs/1610.07236
Autor:
Prajapati, Nirmal, Ranasinghe, Waruna, Rajopadhye, Sanjay, Andonov, Rumen, Djidjev, Hristo, Grosser, Tobias
Publikováno v:
ACM / SIGPLAN Notices; Aug2017, Vol. 52 Issue 8, p163-177, 15p
Autor:
Prajapati, Nirmal, Ranasinghe, Waruna, Tandrapati, Vamshi, Andonov, Rumen, Djidjev, Hristo, Rajopadhye, Sanjay
Publikováno v:
2015 IEEE 20th Conference on Emerging Technologies & Factory Automation (ETFA); 2015, p888-895, 8p
Autor:
Xie, Xing, Ray, Indrakshi, Ranasinghe, Waruna, Gilbert, Philips A., Shashidhara, Pramod, Yadav, Anoop
Publikováno v:
2013 IEEE 33rd International Conference on Distributed Computing Systems Workshops; 2013, p368-373, 6p