Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Ramin Farjad"'
Autor:
Mark Kuemerle, Ramin Farjad, Suresh Subramanian, Bapiraju Vinnakota, Ken Poulton, Halil Cirit, Shahab Ardalan
Publikováno v:
Hot Interconnects
Bunch of Wires (BoW) is a new open die-to-die (D2D) interface. BoW’s objective is to allow designers to gracefully trade-off performance for design and packaging complexity across a wide range of process nodes. BoW bandwidth can range from 80 Gbps
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::858b1b69a1c3ef2f010bdc3f387caf22
https://doi.org/10.1109/hoti51249.2020.00017
https://doi.org/10.1109/hoti51249.2020.00017
Autor:
Ramin Shirani, Ramin Farjad-Rad
Publikováno v:
Hot Chips Symposium
This article consists of a collection of slides from the authors' conference presentation. The ever growing data requirements in the cloud and mobility are creating a bandwidth constraint in global IT infrastructure. In 2012, Aquantia focused on addi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::80a610191b72c3797246569a49aa983c
https://doi.org/10.1109/hotchips.2015.7477466
https://doi.org/10.1109/hotchips.2015.7477466
Autor:
R. Rathi, William J. Dally, R. Senthinathan, Hiok-Tiaq Ng, Trey Greer, M.-J.E. Lee, J. Edmondson, John W. Poulton, J. Tran, A. Nguyen, Ramin Farjad-Rad
Publikováno v:
CICC
A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking ap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::601c792276566dd0b8fd81c870c55a98
https://doi.org/10.1109/jssc.2004.831457
https://doi.org/10.1109/jssc.2004.831457
Autor:
Hiok-Tiaq Ng, Trey Greer, William J. Dally, Ramin Farjad-Rad, John W. Poulton, J. Edmondson, R. Senthinathan, R. Rathi, M.-J.E. Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:2101-2110
A compact (1 mm /spl times/ 160 /spl mu/m) and low-power (80-mW) 0.18-/spl mu/m CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d265a5bd916c1c93eef2c159e579a74d
https://doi.org/10.1109/jssc.2003.818576
https://doi.org/10.1109/jssc.2003.818576
Autor:
Hiok-Tiaq Ng, Trey Greer, M.-J.E. Lee, R. Senthinathan, Ramin Farjad-Rad, William J. Dally, John W. Poulton
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:614-621
This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3282441bc608332a8ef0a17accb1c986
https://doi.org/10.1109/jssc.2003.809519
https://doi.org/10.1109/jssc.2003.809519
Autor:
Hiok-Tiaq Ng, William J. Dally, R. Rathi, John W. Poulton, M.-J.E. Lee, Ramin Farjad-Rad, R. Senthinathan
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:1804-1812
A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design remove
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2baf5299e1b7b4d6e34bacc22cbdc732
https://doi.org/10.1109/jssc.2002.804340
https://doi.org/10.1109/jssc.2002.804340
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:757-764
An 8-Gb/s 0.3-/spl mu/m CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by mu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fb9bc1edfd2491c3b569fa3b19d70f1f
https://doi.org/10.1109/4.841504
https://doi.org/10.1109/4.841504
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:580-585
A serial link transmitter fabricated in a large-scale integrated 0.4-/spl mu/m CMOS process uses multilevel signaling (4-PBM) and a three-tap pre-emphasis filter to reduce intersymbol interference (ISI) caused by channel low-pass effects. Due to the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e677efa9c79f460cbe225aeddbbe84d7
https://doi.org/10.1109/4.760366
https://doi.org/10.1109/4.760366
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:713-722
A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-/spl mu/m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d27fd1e75abbb80fac95aafc1195364
https://doi.org/10.1109/4.668986
https://doi.org/10.1109/4.668986
Autor:
Ahmad R. Tavakoli, Hiok-Tiaq Ng, Ramin Shirani, Ramin Farjad, Friedel Gerfers, David Nguyen, Michael Brown
Publikováno v:
ISSCC
High-density 48-port network switches demand very power-efficient, small form-factor quad PHYs which comply with the IEEE 802.3an transmit PSD and return-loss requirements on the one hand and meet the FCC Class-A specifications on the other hand. We
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::954c76857297447bcc0fe95d9f0c0bbf
https://doi.org/10.1109/isscc.2012.6177069
https://doi.org/10.1109/isscc.2012.6177069