Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Ramesh Arvapalli"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1954-1962
An energy efficient on-die 20-way set associative L3 cache of size 20 MB for the Intel® Xeon® processor E5 family is presented. It is manufactured in the Intel's 32-nm second generation of high-K dielectric metal gate process with 9-copper metal la
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db383bae8ff7a1d5d0806a6468703bbc
https://doi.org/10.1109/jssc.2013.2258815
https://doi.org/10.1109/jssc.2013.2258815
Publikováno v:
CICC
A 20-way set associative 20MB energy efficient L3 this paper. The design uses 0.2119um2 cell and is manufactured in the 32nm second generation of high-K dielectric metal gate process with 9-copper layers. The power efficiency was achieved by employin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f491ac5553b714df01d65daca2ee7b1
https://doi.org/10.1109/cicc.2012.6330624
https://doi.org/10.1109/cicc.2012.6330624